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參數(shù)資料
| 型號(hào)： | L64777 |
| 廠商： | LSI CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Digital Video Broadcasting(DVB)-Compliant,quadrature amplitude modulation (QAM)Modulator(數(shù)字視頻廣播系統(tǒng)適配的積分調(diào)幅調(diào)制器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP120 |
| 封裝： | 32 MM, PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 83/124頁(yè) |
| 文件大小： | 988K |
| 代理商： | L64777 |
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MPEG Transport Stream Multiplexer Signals
5-3
5.2 MPEG Transport Stream Multiplexer Signals
DIN[7:0]
QAM Modulator Parallel/Serial Data In
Serial data enters the L64777 on DIN[0]; parallel data
enters on DIN[7:0]. The modulator samples DIN[7:0] at
the positive edge of ICLK. The DIN[7:0] input accepts
data with any number of invalid bits in between. The
modulator disregards invalid bits or bytes and does not
take them into the input FIFO.
Input
DVALIDIN
Clock Enable Input
When DVALIDIN is active (HIGH), the L64777 accepts
data from DIN[7:0] on a continuous basis. When
DVALIDIN is LOW, data input to the internal FIFO and
internal data processing stops, and the encoder does not
accept new input from the DIN[7:0] pins. DVALIDIN
functions independently of the modulator.
Input
ERRORIN
Error Detection Flag
The ERRORIN pin is asserted to flag uncorrectable
errors. The L64777 checks the ERRORIN status at the
first bit of a frame; then, if required (HIGH = set error bit),
it copies the value of that bit to the MPEG error-indication
bit.
Input
FSTARTIN
External Sync Input
The FSTARTIN pin is asserted to mark the beginning of
an MPEG transport packet by a hardwired signal. If the
incoming bitstream contains no unique sync words, this
pulse must be applied to the L64777. The L64777 forces
synchronization with FSTARTIN pulses into the chip; it
does not flywheel-stabilize synchronization as in the sync
word detection mode. In the sync insertion mode, the
L64777 regenerates the DVB-defined sync information
and inserts it into the QAM Modulator.
Input
ICLK
QAM Modulator Input Clock
ICLK is a positive-edge-triggered clock. The L64777
clocks DIN[7:0], DVALIDIN, ERRORIN, FSTARTIN and
SSTARTIN on the rising edge of ICLK. ICLK is either a
byte clock or a bit clock, depending on the control register
(Register 1) setup for parallel/serial mode.
Input
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