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參數(shù)資料
| 型號(hào)： | L64777 |
| 廠(chǎng)商： | LSI CORP |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | Digital Video Broadcasting(DVB)-Compliant,quadrature amplitude modulation (QAM)Modulator(數(shù)字視頻廣播系統(tǒng)適配的積分調(diào)幅調(diào)制器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP120 |
| 封裝： | 32 MM, PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 50/124頁(yè) |
| 文件大?。?/td> | 988K |
| 代理商： | L64777 |
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2-36
Modulator Architecture
Figure 2.22 NCO Loop Diagram
2.12.2 Acquisition Phase Using the Frequency Measurement Unit
During the acquisition phase, the NCO bases the measurement on the
assumption that the byte clock on the ICLK input has a duration of either
of n
1, n, or n + 1 PCLK cycles and that the input stays within these
bounds for the duration of the measurement. You can program the
duration in multiples of 256-byte clock cycles in the REF_DUR register
(see Section 4.2.7, “Registers 21 and 22,” page 4-14). The NCO control
register (see Section 4.2.3, “Register 14,” page 4-12) can control the start
of the measurement, and the Measurement Done bit in register 13
indicates successful completion. If bit 2 of Register 14 enables an
interrupt, the measurement generates it.
After completion of the measurement, the host reads the number of byte
clock cycles found with the appropriate length of n, n + 1 and n
1 (from
NM_COUNT, N_COUNT, NP_COUNT—see Sections 4.2.10 through
4.2.12), as well as the value of n (from N_PCLK—see Section 4.2.9).
Frequency
Measurement Unit
58
CNT_I
Divider
CNT_O
Divider
NCO
phase_gain
EXOR
Step
OCLK
Interpolator
Ctrl
enable_phase_loop = 1
Byte Clock
If Serial
Virtual FIFO for Automatic
Frequency Acquisition
NPCLK,
N_COUNT, NP_COUNT,
NM_COUNT
ICLK
Threshold
Step Correction
Phase Loop
(for Frequency Selection)
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