參數(shù)資料
型號: KSZ8842-PMQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 67/119頁
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8842-PMQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要屬性: 2 個端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品:
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
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其它名稱: 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
51
M9999-100207-1.5
respond to when receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB,
where the bytes are received from left to right, and the bits within each byte are received right to left (LSB to MSB). The
actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101.
The following table shows the register bit fields.
Bit
Default
R/W
Description
15-0
RW
MARH MAC Address High
The Most significant word of the MAC address
Reserved (Offset 0x0206 - 0x020A
The following table shows the register bit fields.
Bit
Default
R/W
Description
15 – 0
0x0000
RO
Reserved
On-Chip Bus Control Register (Offset 0x0210): OBCR
This register controls the on-chip bus speed for the KSZ8842-PMQL/PMBL. It is used for reduced power consumption
when the external host CPU is running at a slow frequency. The default of the on-chip bus speed is 25MHz. When the
external host CPU is running at a higher clock rate, adjust the on-chip bus for the best performance.
The following table shows the register bit fields.
Bit
Default
R/W
Description
15 – 2
RO
Reserved
1 – 0
0x3
RW
OBSC On-Chip Bus Speed Control
00: 125MHz
01: 62.5MHz
10: 41.66MHz
11: 25MHz
EEPROM Control Register (Offset 0x0212): EEPCR
KSZ8842-PMQL/PMBL supports designs with and without an EEPROM system design. To support an external
EEPROM, tie the EEPROM Enable (EEEN) pin/ball to High; otherwise, tie it to Low or no connect. The KSZ8842-
PMQL/PMBL allows software to access (read and write) the EEPROM directly; that is, the EEPROM access timing can
be fully controlled by the software if the EEPROM Software Access bit 4 in EEPCR is set.
The following table shows the register bit fields.
Bit
Default
R/W
Description
15 – 5
0
RO
Reserved
4
0
RW
EESA EEPROM Software Access
1 = Enable software to access EEPROM through bit 3 to bit 0.
0 = Disable software to access EEPROM.
3
00
RO
EECB EEPROM Status Bits
Bit 3: Data Out from EEPROM. This bit directly reflects the value of the
EEDI pin/ball.
2
00
RW
EECB EEPROM Control Bits
Bit 2: Data In to EEPROM. This bit directly controls the device’s the EEDO
pin/ball.
1
00
RW
EECB EEPROM Control Bits
Bit 1: Serial Clock. This bit directly controls the device’s the EESK pin/ball.
0
00
RW
EECB EEPROM Control Bits
Bit 0: Chip Select. This bit directly controls the device’s the EECS pin/ball.
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