參數(shù)資料
型號(hào): KSZ8842-PMQL-EVAL
廠商: Micrel Inc
文件頁(yè)數(shù): 58/119頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8842-PMQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要屬性: 2 個(gè)端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品:
產(chǎn)品目錄頁(yè)面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名稱: 576-1636
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Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
43
M9999-100207-1.5
Bit
Default
Description
7 – 0
0x00
Interrupt Line
Provides interrupt line routing information. The basic input/output system
(BIOS) writes the routing information into to this field when it initialized and
configures the system.
The value in this field indicates which input of the system interrupt controller is
connected to the KSZ8842-PMQL/PMBL’s interrupt pin/ball. The driver uses
this information to determine priority and vector information. Values in this field
are system architecture specific.
The following table shows the access rules of the register.
Category
Description
Value after hardware reset
0x281401XX
PCI Control & Status Registers
The PCI CSR registers are all 32 bit in Little Endian format. For PCI register Read cycle, the KSZ8842-PMQL/PMBL
allows any different combination of CBEN. For PCI register bus cycles, only byte, word (16-bit), or Dword (32-bit)
accesses are allowed. Any other combinations are illegal, and will be target aborted.
MAC DMA Transmit Control Register (MDTXC Offset 0x0000)
The MAC DMA transmit control register establishes the transmit operating modes and commands for the port. This
register should be one of the last CSRs to be written as part of the transmit initialization.
The following table shows the register bit fields.
Bit
Default
R/W
Description
31 – 30
-
RO
Reserved
29 – 24
0x00
RW
MTBS DMA Transmit Burst Size
This field indicates the maximum number of words to be transferred in one
DMA transaction. If reset, the MAC DMA burst size is limited only by the
amound of data stored in the transmit buffer before issuing a bus request. The
MTBS can be programmed with the following permissible values: 0,1, 2, 4, 8,
16, or 32.
After reset, the MTBS default is 0, i.e., unlimited.
23 – 19
0x00
RO
Reserved
18
0
RW
MTUCG MAC Transmit UDP Checksum Generate
When set, the KSZ8842-PMQL/PMBL will generate correct UDP checksum for
outgoing UDP/IP frames at port.
When this bit is set, ADD CRC should also turn on.
17
0
RW
MTTCG MAC Transmit TCP Checksum Generate
When set, the KSZ8842-PMQL/PMBL will generate correct TCP checksum for
outgoing TCP/IP frames at port.
When this bit is set, ADD CRC should also turn on.
16
0
RW
MTICG MAC Transmit IP Checksum Generate
When set, the KSZ8842-PMQL/PMBL will generate correct IP checksum for
outgoing IP frames at port.
When this bit is set, ADD CRC should also turn on.
15 – 10
0x00
RO
Reserved
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