參數(shù)資料
型號(hào): KSZ8842-PMQL-EVAL
廠商: Micrel Inc
文件頁(yè)數(shù): 51/119頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8842-PMQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要屬性: 2 個(gè)端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品:
產(chǎn)品目錄頁(yè)面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名稱(chēng): 576-1636
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Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
37
M9999-100207-1.5
The following table shows the RDES1 register bit fields.
Bit
Description
31 – 26
Reserved
25
RER Receive End of Ring
When set, indicates that the descriptor list reached its final descriptor. The KSZ8842-
PMQL/PMBL returns to the base address of the list, thus creating a descriptor ring.
24 – 11
Reserved
10 – 0
RBS Receive Buffer Size
Indicates the size, in bytes, of the receive data buffer. If the field is 0, the KSZ8842-
PMQL/PMBL ignores this buffer and moves to the next descriptor.
The buffer size must be a multiple of 4.
The following table shows the RDES2 register bit fields.
Bit
Description
31 – 0
Buffer Address
Indicates the physical memory address of the buffer.
The buffer address must be Word aligned.
The following table shows the RDES3 register bit fields.
Bit
Description
31 – 0
Next Descriptor Address
Indicates the physical memory address of the next descriptor in the descriptor ring.
The buffer address must be Word aligned.
Transmit Descriptors (TDES0-TDES3)
Transmit descriptors must be Word aligned. Each descriptor provides one frame buffer, one byte count field, and
control and status bits.
The following table shows the TDES0 register bit fields.
Bit
Description
31
OWN Own Bit
When set, indicates that the descriptor is owned by the KSZ8842-PMQL/PMBL. When
cleared, indicates that the descriptor is owned by the host. The KSZ8842-PMQL/PMBL
clears this bit either when it completes the frame transmission or when the buffer allocated in
the descriptor is empty.
The ownership bit of the first descriptor of the frame should be set after all subsequent
descriptors belonging to the same frame have been set. This avoids a possible race
condition between the KSZ8842-PMQL/PMBL fetching a descriptor and the driver setting an
ownership bit.
30 – 0
Reserved
The following table shows the TDES1 register bit fields.
Bit
Description
31
IC Interrupt on Completion
When set, the KSZ8842-PMQL/PMBL sets transmit interrupt after the present frame has
been transmitted. It is valid only when last segment is set.
30
FS First Segment
When set, indicates that the buffer contains the first segment of a frame.
29
LS Last Segment
When set, indicates that the buffer contains the last segment of a frame.
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