參數(shù)資料
型號： KSZ8842-PMQL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 29/119頁
文件大小： 0K
描述： BOARD EVALUATION KSZ8842-PMQL
標準包裝： 1
主要目的： 接口，以太網控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8842-PMQL
主要屬性： 2 個端口，100BASE-TX/10BASE-T
次要屬性： 8/16 位接口，LinkMD 線纜診斷
已供物品： 板
產品目錄頁面： 1114 (CN2011-ZH PDF)
相關產品： 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名稱： 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
17
M9999-100207-1.5
Ball
Number
Ball
Name
Type
Ball Function
defines the start of each phase. The clock maximum frequency is 33MHz.
B4
INTRN
Opd
Interrupt Request. Active Low signal to host CPU to request an interrupt when any one of the
interrupt conditions occurs in the registers. This pin should be pull-up externally.
A4
EECS
Opu
EEPROM Chip Select. This signal is used to select an external EEPROM device
C3
P2LED3
Opd
Port 2 LED Indicator
See the description in ball B5, B6 and A6.
A3
EEEN
Ipd
EEPROM Enable
EEPROM is enabled and connected when this pin is pull-up.
EEPROM is disabled when this pin is pull-down or no connect.
B3
P1LED3
Opd
Port 1 LED indicator
See the description in ball C7, A7 and B7.
B2
EEDO
Opd
EEPROM Data Out:
This pin is connected to DI input of the serial EEPROM.
A2
EESK
Opd
EEPROM Serial Clock:
A 4
s serial output clock to load configuration data from the serial EEPROM.
A1
EEDI
Ipd
EEPROM Data In:
This pin is connected to DO output of the serial EEPROM.
B1
PWRDN
Ipu
Full-chip power-down. Active Low.
C1
RXP1
I/O
Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)
C2
RXM1
I/O
Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)
D1
TXP1
I/O
Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)
D2
TXM1
I/O
Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)
F2
RXM2
I/O
Port 2 physical receive (MDI) or transmit (MDIX)signal (- differential)
F1
RXP2
I/O
Port 2 physical receive(MDI) or transmit (MDIX) signal (+ differential)
G2
TXM2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
G1
TXP2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
G3
ISET
O
Set physical transmit output current.
Pull-down this ball with a 3.01K 1% resistor.
H1
X1
I
H2
X2
O
25MHz crystal/oscillator clock connections
Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant
oscillator and X2 is a no connect.
Note: Clock is
± 50ppm for both crystal and oscillator.
J1
RSTN
Ipu
Hardware Reset, Active Low
RSTN will cause the KSZ8842-PMBL to reset all of its functional blocks. RSTN must be
asserted for a minimum duration of 10 ms.
J2
PAR
O
PCI Parity
Even parity computed for PAD [31:0] and CBE[3:0]N, master drives PAR for address and
write data phase, target drives PAR for read data phase.
K1
FRAMEN
I/O
PCI Cycle Frame
This signal is asserted low to indicate the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of the transaction in a
bus master mode. As a target, the device monitors this signal before decoding the address to
check if the current transaction is addressed to it.
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