參數(shù)資料
型號(hào): KSZ8842-PMQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 57/119頁
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8842-PMQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要屬性: 2 個(gè)端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品:
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名稱: 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
42
M9999-100207-1.5
Configuration Base Memory Address Register (CBMA Offset 10H)
The CBMA register specifies the base memory address for accessing the KSZ8842-PMQL/PMBL CSRs. This register
must be initialized prior to accessing any CSR with memory access.
The following table shows the CBMA register bit fields.
Bit
Default
Description
31 - 11
0
Configuration Base Memory Address
Defines the base address assigned for mapping the KSZ8841-PMQL/PMBL
CSRs.
10 - 1
0
This field value is 0 when read.
0
Memory Space Indicator
Determines that the register maps into the Memory space.
The value in this field is 0.
This is a read-only field.
Subsystem ID Register (CSID Offset 2CH)
The CSID register is a read-only 32-bit register. The content of the CSID is loaded from the EEPROM after a hardware
reset. The loading period lasts at least 27,400 PCI cycles when the system is in 33MHz mode, and starts 50 cycles
after hardware reset deassertion. If the host accesses the CSID before its content is loaded from the EEPROM, the
KSZ8842-PMQL/PMBL responds with retry termination on the PCI bus.
The following table shows the CSID register bit fields.
Bit
Description
31 – 16
Subsystem ID
Indicates a 16-bit field containing the subsystem ID.
15 – 0
Subsystem Vendor ID
Indicates a 16-bit field containing the subsystem vendor ID.
The following table shows the access rules of the register.
Configuration Interrupt Register (CFIT Offset 3CH)
The CFIT register is divided into two sections: the interrupt line and the interrupt pin/ball. CFIT configures both the
system’s interrupt and the KSZ8842-PMQL/PMBL interrupt pin/ball connection.
The following table shows the CFIT register bit fields.
Bit
Default
Description
31 – 24
0x28
MAX_LAT
This field indicates how often the device needs to gain access to the PCI bus.
Time unit is equal to 0.25s, assuming a PCI clock frequency of 33 MHz.
The value after a hardware reset is 28H (10s).
23 – 16
0x14
MIN_GNT
This field indicates the burst period length that the device needs. Time unit is
equal to 0.25s, assuming a PCI clock frequency of 33 MHz.
The value after a hardware reset is 14H (5s).
15 – 8
0x01
Interrupt Pin/ball
Indicates which interrupt pin/ball that the KSZ8842-PMQL/PMBL uses. The
KSZ8842-PMQL/PMBL uses INTA# and the read value is 1H.
Category
Description
Value after hardware reset
Read from EEPROM.
Write access rules
Write has no effect on the KSZ8842-PMQL/PMBL.
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