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參數(shù)資料
| 型號(hào)： | KM29W8000T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 8 Bit NAND Flash Memory(1M x 8 位 NAND閃速存儲(chǔ)器) |
| 中文描述： | 100萬× 8位NAND快閃記憶體（1米× 8位的NAND閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 266K |
| 代理商： | KM29W8000T |
KM29W8000T, KM29W8000IT
FLASH MEMORY
8
AC Characteristics for Operation
NOTE
: 1. If CE goes high within 30ns after the rising edge of the last RE, R/B will not return to V
OL
.
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
3. To break the sequential read cycle, CE must be held high for longer time than tCEH.
Parameter
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
t
R
-
10
μ
s
ALE to RE Delay
t
AR
150
-
ns
ALE to RE Delay( ID Read )
t
AR1
200
-
ns
CE to RE Delay( ID Read )
t
CR
200
-
ns
Ready to RE Low
t
RR
20
-
ns
WE High to Busy
t
WB
-
200
ns
Read Cycle Time
t
RC
80
-
ns
RE Access Time
t
REA
-
45
ns
RE High to Output Hi-Z
t
RHZ
5
20
ns
CE High to Output Hi-Z
t
CHZ
-
30
ns
RE High Hold Time
t
REH
20
-
ns
Output Hi-Z to RE Low
t
IR
0
-
ns
Last RE High to Busy(at sequential read)
t
RB
-
200
ns
CE High to Ready(in case of interception by at read)
(1)
t
CRY
-
100+tr(R/B)
(2)
ns
CE High Hold Time(at the last serial read)
(3)
t
CEH
250
-
ns
RE Low to Status Output
t
RSTO
-
45
ns
CE Low to Status Output
t
CSTO
-
55
ns
WE High to RE Low
t
WHR
50
-
ns
Device Resetting Time
(Read/Program/Erase)
t
RST
-
5/10/500
μ
s
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE Set-up Time
t
CLS
20
-
ns
CLE Hold Time
t
CLH
40
-
ns
CE Setup Time
t
CS
20
-
ns
CE Hold Time
t
CH
40
-
ns
WE Pulse Width
t
WP
40
-
ns
ALE Setup Time
t
ALS
20
-
ns
ALE Hold Time
t
ALH
40
-
ns
Data Setup Time
t
DS
30
-
ns
Data Hold Time
t
DH
20
-
ns
Write Cycle Time
t
WC
80
-
ns
WE High Hold Time
t
WH
20
-
ns
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