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參數(shù)資料
| 型號(hào)： | KM29W8000T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 8 Bit NAND Flash Memory(1M x 8 位 NAND閃速存儲(chǔ)器) |
| 中文描述： | 100萬(wàn)× 8位NAND快閃記憶體（1米× 8位的NAND閃速存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 2/23頁(yè) |
| 文件大?。?/td> | 266K |
| 代理商： | KM29W8000T |
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KM29W8000T, KM29W8000IT
FLASH MEMORY
2
1M x 8 Bit NAND Flash Memory
The KM29W8000 is a 1M(1,048,576)x8bit NAND Flash Mem-
ory with a spare 32K(32,768)x8bit. Its NAND cell provides the
most cost-effective solution for the solid state mass storage
market. A program operation programs the 264-byte page in
typically 250
μ
s and an erase operation can be performed in
typically 2ms on a 4K-byte block.
Data in the page can be read out at 80ns cycle time per byte.
The I/O pins serve as the ports for address and data input/out-
put as well as command inputs. The on-chip write controller
automates all program and erase system functions, including
pulse repetition, where required, and internal verify and margin-
ing of data. Even the write-intensive systems can take advan-
tage of the KM29W8000 extended reliability of 1,000,000
program/erase cycles by providing either ECC(Error Correction
Code) or real time mapping-out algorithm. These algorithms
have been implemented in many mass storage applications
and also the spare 8bytes of a page combined with the other
256 bytes can be utilized by system-level ECC.
The KM29W8000 is an optimum solution for large nonvolatile
storage application such as solid state storage, digital voice
recorder, digital still camera and other portable applications
requiring nonvolatility.
GENERAL DESCRIPTION
FEATURES
Voltage supply : 2.7V ~ 5.5V
Organization
- Memory Cell Array : (1M + 32K)bit x 8bit
- Data Register : (256 + 8)bit x8bit
Automatic Program and Erase(Typical)
- Page Program : (256 + 8)Byte in 250
μ
s
- Block Erase : (4K + 128)Byte in 2ms
- Status Register
264-Byte Page Read Operation
- Random Access : 10
μ
s(Max.)
- Serial Page Access : 80ns(Min.)
System Performance Enhancement
- Ready/ Busy Status Output
Command/Address/Data Multiplexed I/O port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 1M Program/Erase Cycles
- Data Retention : 10 years
Command Register Operation
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
PIN CONFIGURATION
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
I/O4
I/O5
I/O6
I/O7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
VCC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44(40) TSOP (II)
STANDARD TYPE
NOTE
: Connect all V
CC
and V
SS
pins of each device to power supply outputs.
Do NOT leave V
CC
or V
SS
disconnected.
Pin Name
Pin Function
I/O
0
~I/O
7
Data Inputs/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
GND
Ground Input
R/B
Ready/Busy output
V
CC
Power(2.7V ~ 5.5V)
V
SS
Ground
N.C
No Connection
PIN DESCRIPTION
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