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參數資料
| 型號： | KM29W8000T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 8 Bit NAND Flash Memory(1M x 8 位 NAND閃速存儲器) |
| 中文描述： | 100萬× 8位NAND快閃記憶體（1米× 8位的NAND閃速存儲器） |
| 文件頁數： | 20/23頁 |
| 文件大?。?/td> | 266K |
| 代理商： | KM29W8000T |
KM29W8000T, KM29W8000IT
FLASH MEMORY
20
Figure 8. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block(4K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60H). Only address A
12
to A
19
is valid while A
8
to A
11
is ignored. The Erase Confirm command(D0H) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noises conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse
repetition where required. If an erase operation error is detected, the internal verify is halted and erase operation is termina ted. When
the erase operation is complete, the Write Status Bit(I/O
0
) may be checked.
Figure 8 details the sequence.
60H
Block Add. : A
8
~ A
19
I/O
0
~
7
R/B
Address Input(2Cycle)
I/O
0
Pass
D0H
70H
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether
the program or erase operation is completed successfully. After writing 70H command to the command register, a read cycle output s
the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/ B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random r ead
cycle, a read command(00H or 50H) should be given before sequential page read cycle.
SR
Status
Definition
I/O
0
Program / Erase
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O
1
Reserved for Future
Use
"0"
I/O
2
"0"
I/O
3
"0"
I/O
4
"0"
I/O
5
"0"
I/O
6
Device Operation
"0" : Busy "1" : Ready
I/O
7
Write Protect
"0" : Protected "1" : Not Protected
Table2. Status Register Definition
t
BERS
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