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參數(shù)資料
| 型號： | K4N56163QF-GC37 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit gDDR2 SDRAM |
| 中文描述： | 片256Mbit GDDR2 SDRAM的 |
| 文件頁數(shù)： | 65/73頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | K4N56163QF-GC37 |
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- 65 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
Input Clock Frequency Change during Precharge Power Down
gDDR2 SDRAM input clock frequency can be changed under following condition:
gDDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A min-
imum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock fre-
quency is allowed to change only within minimum and maximum operating frequency specified for the particular speed
grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock fre-
quency is changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL
must be RESET via EMRS after precharge power down exit. Depending on new clock frequency an additional MRS com-
mand may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock period, ODT must remain off. After
the DLL lock time, the DRAM is ready to operate with new clock frequency.
CK
CKE
T0
T4
Tx+1
Ty
Ty+1
Ty+2
T1
T2
Tx
CK
Valid
DLL
RESET
NOP
200 Clocks
Frequency Change
Occurs here
Ty+3
Tz
NOP
NOP
NOP
NOP
tRP
Clock Frequency Change in Precharge Power Down Mode
tXP
tAOFD
Stable new clock
before power down exit
ODT is off during
DLL RESET
Minimum 2 clocks
required before
changing frequency
ODT
CMD
Ty+4
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