參數(shù)資料
型號(hào)： K4J55323QF-GC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mbit GDDR3 SDRAM
中文描述： 片256Mbit GDDR3 SDRAM的
文件頁(yè)數(shù)： 45/49頁(yè)
文件大?。?/td> 1027K
代理商： K4J55323QF-GC
- 45 -
256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
CLOCK INPUT OPERATING CONDITIONS
Recommended operating conditions (
0
°
C
≤
Tc
≤85°
C ; VDD=2.0V + 0.1V, VDDQ=2.0V + 0.1V
)
Note : 1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ
2. For AC operations, all DC clock requirements must be satisfied as well.
3. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.
4.
VID is the magnitude of the difference between the input level in CK and the input level on /CK.
5. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross;
the input reference level for signals other than CK and /CK is VREF.
6. CK and /CK input slew rate must be > 3V/ns
Parameter/ Condition
Symbol
Min
Max
Unit Note
Clock Input Mid-Point Voltage ; CK and /CK
V
MP(DC)
1.16
1.36
V
1,2,3
Clock Input Voltage Level; CK and /CK
V
IN(DC)
0.42
V
DDQ
+ 0.3
V
2
Clock Input Differential Voltage ; CK and /CK
V
ID(DC)
0.22
V
DDQ
+ 0.5
V
2,4
Clock Input Differential Voltage ; CK and /CK
V
ID(AC)
0.22
V
DDQ
+ 0.3
V
4
Clock Input Crossing Point Voltage ; CK and /CK
V
IX(AC)
V
REF
- 0.15
V
REF
+ 0.15
V
3
Note : 1 . Outputs measured into equivalent load of 10pf at a driver impedance of 40
.
ZQ
GDDR3
V
REF
240
1.26V
Z
0
=60
60
V
DDQ
10pf
Output Load Circuit
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