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參數(shù)資料
| 型號： | K4J55323QF-GC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit GDDR3 SDRAM |
| 中文描述： | 片256Mbit GDDR3 SDRAM的 |
| 文件頁數(shù)： | 10/49頁 |
| 文件大小： | 1027K |
| 代理商： | K4J55323QF-GC |
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256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS
latency, addressing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of dif-
ferent applications. The default value of the mode register is not defined, therefore the mode register must be written after
EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3
SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins
A
0
~ A
11
and BA
0
, BA
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum six
clock cycles are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state.
The mode register is divided into various fields depending on functionality. The Burst length uses A
0
~ A
2
. CAS latency
(read latency from column address) uses A
4
~ A
6
. A
7
is used for test mode. A
8
is used for DLL reset. A
9
~ A
11
are used
for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies.
MODE REGISTER SET(MRS)
CAS Latency
A
6
0
0
0
0
1
1
1
1
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
CAS Latency
8
9
Reserved
Reserved
Reserved
5
6
7
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Test Mode
A
7
0
1
mode
Normal
Test
Burst Type
A
3
0
1
Burst Type
Sequential
Reserved
DLL
A
8
0
1
DLL Reset
No
Yes
0
0
WL
DLL
TM
CAS Latency
BT
Burst Length
Burst Length
A
2
0
0
0
0
1
1
1
1
A
1
0
0
1
1
0
0
1
1
A
0
0
1
0
1
0
1
0
1
Burst Length
Reserved
Reserved
4
Reserved
Reserved
Reserved
Reserved
Reserved
BA
0
0
1
A
n
~ A
0
MRS
EMRS
Write Latency
A
11
0
0
0
0
1
1
1
1
A
10
0
0
1
1
0
0
1
1
A
9
0
1
0
1
0
1
0
1
Write Latency
Reserved
1
2
3
4
5
6
Reserved
相關PDF資料 |
PDF描述 |
|---|---|
| K4J55323QF-GC14 | 256Mbit GDDR3 SDRAM |
| K4J55323QF-GC15 | 256Mbit GDDR3 SDRAM |
| K4J55323QF-GC16 | 256Mbit GDDR3 SDRAM |
| K4J55323QF-GC20 | 256Mbit GDDR3 SDRAM |
| K4M51163LE | 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K4J55323QF-GC14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QF-GC15 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QF-GC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QF-GC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
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