參數(shù)資料
型號: ISPPAC10-01PI
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: In-System Programmable Analog Circuit
中文描述: SPECIALTY ANALOG CIRCUIT, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 22/23頁
文件大?。?/td> 415K
代理商: ISPPAC10-01PI
Specifications
ispPAC10
22
The last Lattice instruction is
UBE
(user bulk erase).
Operation of the device is interrupted during UBE, after
which all inputs are disconnected and all outputs driven
to VREF
OUT
(2.5V). To economize internal circuitry,
programming can only be selectively done in one direc-
tion (from zeroes to ones). The UBE is used to return all
user bits to a zero state at the same time. A UBE usually
proceeds a PRGUSR operation, otherwise one to zero
changes would not be implemented. It can also be used
to erase all configuration information from a device and
is the default condition of parts shipped from the factory.
The same programming constraints apply to UBE as for
PRGUSR. The bit code for this instruction is shown in
Table 2.
The ADDUSR, BYPASS, EXTEST, IDCODE and
SAMPLE/PRELOAD instructions are all executed in the
Update-IR state. Other instructions: PRGUSR, VERUSR
and UBE are executed upon entry of the Run-Test/Idle
state.
It is recommended that when all serial interface opera-
tions are completed, the TAP controller be reset and left
in the Test-Logic-Reset state (the power-up default) and
the TCK and TMS inputs idled. This will insure the best
analog performance possible by minimizing the effects of
digital logic
feed-through.
IEEE Standard 1149.1 Interface (Continued)
相關(guān)PDF資料
PDF描述
ISPPAC10-01SI In-System Programmable Analog Circuit
ISPPAC20 In-System Programmable Analog Circuit
ISPPAC20-01J In-System Programmable Analog Circuit
ISPPAC20-01JI In-System Programmable Analog Circuit
ISPPAC30 In-System Programmable Analog Circuit
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ISPPAC20 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit
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