- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384545 > ISPPAC10-01PI (LATTICE SEMICONDUCTOR CORP) In-System Programmable Analog Circuit PDF資料下載
參數(shù)資料
| 型號： | ISPPAC10-01PI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 415K |
| 代理商： | ISPPAC10-01PI |
Specifications
ispPAC10
13
this term is eliminated. The level of attainable attenuation
is as low as 1/11 (-20.8dB) with R
F
enabled or
1/10 (-20dB) with R
F
disabled.
When configuring a PACblock to attenuate, it is neces-
sary to increase the value of feedback capacitance to
maintain stability. Increasing feedback capacitance has
the same beneficial effect as for a discrete op amp: It
increases the network
’
s phase margin which assists in
maintaining stability.
Using VREF
OUT
The VREF
OUT
output is high impedance and it should be
buffered when used as a reference. A PACblock can be
made into a VREF
OUT
buffer as shown in Figure 9. The
PACblock inputs are left unconnected and the feedback
closed. In this condition the input amplifiers are tied to
VREF
OUT
and the output amplifier
’
s outputs are thus
forced to VREF
OUT
or 2.5V. Either output is now a
VREF
OUT
voltage source. This reference has the same
drive capabilities of any ispPAC10 output. However, do
not short the two outputs together. There is a small
potential difference between them which will cause a
steady state current to flow, thus needlessly dissipating
power.
Figure 9. PACblock as VREF
OUT
Buffer
1
1.07pF
OA1
IA1
IA2
PACblock 1
IN1
OUT1
2.5V
-1
OUT1=2.5V
Unconnected
It is not always necessary to buffer the VREF
OUT
output.
If it is used to reference a high impedance source, i.e.,
one that does not require more than 10
μ
A, then it can be
directly connected. An example is shifting the DC level of
a signal connected to the input of a PACblock. In this
case, the signal is AC coupled and
“
terminated
”
in
VREF
OUT
through a minimum total resistance of 100k
.
Referring to Figure 10b, if R
IN
is greater than 200k
then
the VREF
OUT
pin may be used without buffering.
Interfacing
When used in a single-supply system where the system
common mode voltage is near V
S
/2, signals may be
directly connected to the ispPAC10 input. If the input
signal does not have such a DC bias, then one needs to
be added to the signal in order to accommodate the input
requirements for the ispPAC10. A DC coupled bias can
be added to a signal by using a voltage divider circuit as
shown for one-half of the differential input in Figure 10a.
Normally the choice for the reference DC voltage is the
supply voltage, but other values may be used if neces-
sary (and available).
Figure 10a. DC Biasing an Input Signal
2
1
1
OUT
R
+
2
1
2
SE
IN
R
R
VREF
R
R
R
V
V
+
+
=
+
V
IN+
*
V
SE
R
1
R
2
*Single-Ended V
SE
:
Connect to VREF
or
other DC Reference.
*Differential V
:
Duplicate Vin+ Network
on Vin-.
VREF
OUT
V
IN-
Where DC coupling is not required, the input signal may
be AC coupled as shown in Figure 10b. This circuit forms
a high pass filter with a cutoff frequency of 1/(2
π
RC) and
adds the necessary DC bias to the signal to accommo-
date the ispPAC10 input requirements. The DC reference
should equal V
S
/2, making VREF
OUT
the natural choice.
The minimum resistance when using the VREF
OUT
buffer
circuit of Figure 9 is 600
; when using the VREF
OUT
output pin it is 200k
(as discussed earlier).
Theory of Operation (Continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC10-01SI | In-System Programmable Analog Circuit |
| ISPPAC20 | In-System Programmable Analog Circuit |
| ISPPAC20-01J | In-System Programmable Analog Circuit |
| ISPPAC20-01JI | In-System Programmable Analog Circuit |
| ISPPAC30 | In-System Programmable Analog Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC10-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC20 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC20-01J | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC20-01JI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC20-01TI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。