9 FN7911.2 April 25, 2013 LVDS Inputs SYNCP, SYNCN Setup Time (with Respect to the Positive Edge of CLKP) t
參數(shù)資料
型號(hào)： ISLA224S20IR1Z
廠商： Intersil
文件頁(yè)數(shù)： 38/38頁(yè)
文件大?。?/td> 0K
描述： IC ADC
標(biāo)準(zhǔn)包裝： 1
系列： *
ISLA224S
9
FN7911.2
April 25, 2013
LVDS Inputs
SYNCP, SYNCN Setup Time (with Respect to the Positive Edge of
CLKP)
tRSTS
AVDD,
OVDD = 1.7V to
1.9V, TA = -40°C
to +85°C
400
75
ps
SYNCP, SYNCN Hold Time (with respect to the positive edge of
CLKP)
tRSTH
AVDD,
OVDD = 1.7V to
1.9V, TA = -40°C
to +85°C
150
350
ps
CML Outputs
Output Rise Time
tR
165
ps
Output Fall Time
tF
145
ps
Data Output Duty Cycle
50
%
Differential Output Resistance
100
Differential Output Voltage (Note 13)
760
mVP-P
SPI INTERFACE (Notes 14, 15)
SCLK Period
t
CLK
Write Operation
7
cycles
tCLK
Read Operation
16
cycles
CSB
↓ to SCLK↑ Setup Time
tS
Read or Write
2
cycles
CSB
↑ after SCLK↑ Hold Time
tH
Read or Write
5
cycles
Data Valid to SCLK
↑ Setup Time
tDS
Read or Write
6
cycles
Data Valid after SCLK
↑ Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK
↓ Time
tDVR
Read
4
cycles
NOTES:
11. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
12. The synchronous clock divider reset function is available as a (SPI-programmable) overload on the SYNC input.
13. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak single-ended swing is 1/2 of the differential swing.
14. The SPI interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be
scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
15. The SPI may operate asynchronously with respect to the ADC sample clock.
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITION
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
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