33 FN7911.2 April 25, 2013 De vi ce T est C0 test_io Output Test Mode [7:4] JESD Test User Test Mode [2:0] User Test Mode (Single ADC " />
參數(shù)資料
型號(hào)： ISLA224S20IR1Z
廠商： Intersil
文件頁(yè)數(shù)： 27/38頁(yè)
文件大?。?/td> 0K
描述： IC ADC
標(biāo)準(zhǔn)包裝： 1
系列： *
ISLA224S
33
FN7911.2
April 25, 2013
De
vi
ce
T
est
C0
test_io
Output Test Mode [7:4]
JESD Test
User Test Mode [2:0]
User Test Mode (Single ADC
products only)
0 = user pattern 1 only
1 = cycle pattern 1 through 2
2 = cycle pattern 1 through 3
3 = cycle pattern 1 through 4
4 = cycle pattern 1 through 5
5 = cycle pattern 1 through 6
6 = cycle pattern 1 through 7
7 = cycle pattern 1 through 8
User Test Mode (Dual and
interleaved ADC products only)
0 = cycle pattern 1 through 2
1 = cycle pattern 1 through 4
2 = cycle pattern 1 through 6
3 = cycle pattern 1 through 8
4 -7 = NA
00h
<7:4>=Output Test, <3> = JESD Test
JESD Test=0
Output Test =
0x0= Output Test Mode Off. During calibration MSB
justified constant output 0xCCCC
0x1 = Midscale adjusted by numeric format
0x2 = Plus full scale, adjusted by numeric format
0x3 = Minus full scale adjusted by numeric format
0x4 = Checkboard output - 0xAAAA, 0x5555
0x5 = reserved
0x6 = reserved
0x7 = 0xFFFF, 0x0000 all on pattern
0x8 = User pattern 8 deep, MSB justified with output
0x9 = reserved
0xA, Count-up ramp
0xB, PRBS-9
0xC, PRBS-15
0xD, PRBS-23
0xE, PRBS-31
0xF = reserved
JESD Test=1
Output Test =
0x0 =Link Layer Repeat K28.5+Lane Alignment Sequence
0x1, Link Layer Repeat K28.5
0x2, Link Layer Repeat D21.5
0x3, Link Layer Repeat K28.7
0x4, Link Layer PRBS-7
0x5, Link Layer PRBS-23
0x6, Link Layer All Zeros
0x7, Link Layer All Ones
0x8-0xE, reserved
0xF, JESD204 section 5.1.6.2 Transport Layer Test Pattern
C1
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C2
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C3
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C4
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C5
user_patt3_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C6
user_patt3_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C7
user_patt4_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C8
user_patt4_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C9
user_patt5_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CA
user_patt5_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CB
user_patt6_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CC
user_patt6_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CD
user_patt7_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CE
user_patt7_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CF
user_patt8_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
D0
user_patt8_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
D1-DE
Reserved
SPI Memory Map (Continued)
ADDR.
(Hex)
PARAMETER NAME
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
DEF. VALUE
(HEX)
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