21 FN7911.2 April 25, 2013 To maximize flexibility at the system level, two transport layer packing modes are supported: simple and ef" />
參數(shù)資料
型號(hào)： ISLA224S20IR1Z
廠商： Intersil
文件頁(yè)數(shù)： 14/38頁(yè)
文件大?。?/td> 0K
描述： IC ADC
標(biāo)準(zhǔn)包裝： 1
系列： *
ISLA224S
21
FN7911.2
April 25, 2013
To maximize flexibility at the system level, two transport layer
packing modes are supported: simple and efficient. These two
modes allow the system designer flexibility to trade off between
the number of lanes to support a given throughput, the data rate
of these lanes, and the complexity of the receiver. This translates
directly into providing system level trade-offs between cost,
power, and resource usage of the receiver and complexity of the
solution.
Simple mode packs informationless bits onto each ADC sample
to form full 16-bit data. In simple mode packing, the frame clock
and ADC sample clock are the same frequency, easing frequency
scaling requirements at the system level, but decreasing the
payload efficiency of the lanes. Decreased payload efficiency of
the lanes increases the lane data rate required to support a given
throughput, and may require additional lanes to support a given
configuration. The degree of payload efficiency loss is dependent
on the ADC resolution.
Efficient mode packs sequential ADC samples into a contiguous
block of an integer number of octets, and then slices the block
into the octets for transport. This mode always achieves the
theoretical maximum payload of the lanes (80%) regardless of
the resolution of the ADC and the number of lanes used. This
mode provides the minimum number of lanes at the minimum
data rate that is theoretically possible given the 8b/10b
encoding used in JESD204 systems. In efficient packing mode,
frame clock and the ADC sample clock have an M/N relationship,
where M and N are small integers and vary depending on the
ADC resolution and number of lanes selected. Efficient mode
packing may require additional frequency scaling elements
(internal FPGA PLLs or discrete frequency scaling devices) to
generate the frame clock for the receiving device.
The default configuration for this device is efficient packing
mode. Reconfiguration into the simple packing mode is
accomplished by programming the JESD204 parameters via the
SPI bus. See Table 5 for the full list of parameters values for each
mode and product. Via SPI, the JESD204 transmitter is highly
configurable, supporting efficient to simple mode packing
reconfiguration as well as “downgrading” a given product’s
JESD204 interface. For example, reconfiguring a 3-lane product
into 2 lanes (with each running faster than with 3 lanes), or
reducing the resolution of the ADC(s) to slow down the lane data
rate in systems where the full ADC resolution is not required, are
supported. Please contact Intersil sales support for a full list of
downgradeable configurations that are supported.
Signal integrity plots, including data eye, BER bathtub curves,
and edge histogram plots versus lane data rate can be found in
Initial Lane Alignment
The link initialization process is started by asserting the SYNC~
signal to the ADC device. This assertion causes the JESD204
transmitter to generate comma characters, which are used by
the receiver to accomplish code group synchronization (bit and
octet alignment, respectively). Once code group synchronization
is detected in the receiver, it de-asserts the SYNC~ signal,
causing the JESD204 transmitter to generate the initial lane
alignment sequence (ILA). The ILA is comprised of 4
multi-frames of data in a standard format, with the length of
each multi-frame determined by the K parameter as
programmed into the SPI JESD204 parameter table. The ILA
includes standard control character markers that can be used to
perform channel bonding in the receiving device if desired. The
2nd multi-frame includes the full JESD204 parameter data,
FIGURE 50. SERDES TRANSMITTER BLOCK DIAGRAM
Sample
Clock
Sample Data
Transport
Layer
Scrambler
1+x
14+x15
Encoder
8/10
Link Layer
SYNC
PLL
Multiply
- Code group Synchronization
- Alignment Characters
- Initial Lane Synchronization
- Etc
SER
Logic
Lane 0
Link Layer
SERDES Block
Lane 1
Link Layer
Lane 2
Sample Data
Analog
Input
Analog
Input
Clock
Management
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