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參數(shù)資料
| 型號： | ISLA224S20IR1Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 22/38頁 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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ISLA224S
29
FN7911.2
April 25, 2013
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
ADDRESS 0xDF - 0xF3: JESD204 REGISTERS
Address 0xDF-0xEE: JESD204 Parameter
INTERFACE
This set of registers controls the JESD204 transmitter
configuration. By programming these parameters, the system
can select between efficient and simple packing, select the
number of powered up SERDES lanes, choose the ADC resolution
transmitted, and so on. The JESD204 parameters for standard
dual channel products are shown in Table 5. This is a small
subset of the total number of configurations supported; contact
the factory for details.
0xE0 through 0xED are the JESD204 parameter registers. These
parameters are written to set the transport layer mapping of the
JESD204 transmitter in this product family. These registers can
be written to shift between efficient and simple packing, to
enable or bypass scrambling, and to reduce the number of
powered up lanes used in the link. Each speed graded product
allows downgrading of the JESD204 link (such as reducing the
number of lanes, reducing the converter resolution, etc), but not
upgrading. These parameters are communicated on every lane
of the link during the 2nd multi-frame of the initial lane
alignment sequence, and therefore can be used by a generic
JESD204 receiver the supports the given configuration. See the
JESD204 specification for additional information on how these
registers are used in a JESD204 system, including encoding
rules.
ADDRESS 0XDF: JESD204_UPDATE_CONFIG_START
Bit 0 update_start
This self-resetting bit is used to indicate that some or all the
JESD204 parameters (addresses 0xE0 through 0xED) are going
to be written. Writing a ‘1’ to this bit will hold the JESD204 PLL
and transmitter in a reset state while these parameters are
written, because these parameters can affect the transmitter’s
dynamic behavior (such as modifying the PLL’s frequency
multiplication). The bit will automatically reset to a ‘0’ once a ‘1’
is written to address 0xEE Bit[0] “update_config W1TC”. The
recommended sequence for modifying the JESD204 transmitter
is numbered as follows:
1. Write a ‘1’ to 0xDF Bit[0]
2. Write some or all modified values to 0xE0 through 0xEC
3. Write a ‘1’ to 0xEE Bit[0]. Note: 0xDF Bit[0] and 0xEE Bit[0] will
automatically be reset to a ‘0’ once configuration has been
applied to the circuitry.
ADDRESS 0XE0: JESD204_CONFIG_0
Bits 7:0 “DID”, JESD204 Device ID number.
ADDRESS 0XE1: JESD204_CONFIG_1
Bits 3:0 “BID”, JESD204 Bank ID.
ADDRESS 0XE2: JESD204_CONFIG_2
Bits 4:0 “LID” JESD204 Lane ID.
ADDRESS 0XE3: JESD204_CONFIG_3
Bit 7 “SCR”, JESD204 SCR controls if scrambling across the
SERDES lane(s) is enabled (‘1’ means enabled).
Bits 4:0 “L”, JESD204 L is the number of SERDES lanes in the
link.
ADDRESS 0XE4: JESD204_CONFIG_4
Bits 7:0 “F”, JESD204 Number of octets per frame period.
ADDRESS 0XE5: JESD204_CONFIG_5
Bits 4:0 “K” JESD204 Number of frame periods per multi-frame
period. This product family supports the full programmable range
of K (decimal 0 through 31), although note that the JESD204
standard dictates a minimum number for this parameter that is
configuration dependent.
ADDRESS 0XE6: JESD204_CONFIG_6
Bits 7:0 “M” JESD204 Number of converters per device.
ADDRESS 0XE7: JESD204_CONFIG_7
Bits 7:6 “CS”, JESD204 CS is the number of control bits per
sample (Always ‘0’ for this product family).
Bits 4:0 “N”, JESD204 N is the converter resolution.
ADDRESS 0XE8: JESD204_CONFIG_8
Bits 7:5 "SUBCLASSV" JESDS204 Device Subclass Version
000 - Subclass 0
001 - Subclass 1 (not supported in this product family)
010- Subclass 2
Bits 4:0 "N'", JESD204 total number of bits per sample.
ADDRESS 0XE9: JESD204_CONFIG_9
Bits 7:5 "JESDV" JESDS204 Version
000 - JESD204A
001 - JESD204B
Bits 4:0 "S", JESD204 number of samples per converter per
frame.
ADDRESS 0XEA: JESD204_CONFIG_10
Bit 7 “HD”, JESD204 HD indicates if a converter’s sample can be
split across multiple lanes in the link (always ‘0’ for this product
family).
Bits 4:0 “CF”, JESD204 CF is the number of control fames per
frame clock (always ‘0’ for this product family).
ADDRESS 0XEB: JESD204_CONFIG_11
Bits 7:0 “RES1”, JESD204 reserved for future use.
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