參數(shù)資料
型號(hào)： ISL5416KIZ
廠商： INTERSIL CORP
元件分類(lèi)： 無(wú)繩電話(huà)/電話(huà)
英文描述： Four-Channel Wideband Programmable DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA256
封裝： 17 X 17 MM, LEAD FREE, PLASTIC, BGA-256
文件頁(yè)數(shù)： 43/71頁(yè)
文件大?。?/td> 1128K
代理商： ISL5416KIZ
43
14
TIME USING CLOCKS/SAMPLES.
Count intervals and delays using clocks or input enables.
1 = clocks.
0 = input enables.
13:11
UPPER LIMIT.
Upper attenuator control limit, 0 to 42 dB in 6 dB steps.
000 = 0 dB.
111 = 42 dB.
10:8
LOWER LIMIT.
Lower attenuator control limit, 0 to 42 dB in 6 dB steps.
000 = 0 dB.
111 = 42 dB.
7:4
NORMALIZATION SHIFT/DIVIDE SELECT.
Normalizing shifter control. Divides the integrated magnitude by 2
N
prior to threshold comparison:
accumulator input bits:
2
0
. . . 2
-15
accumulator output bits:
2
16
. . . 2
-15
0000 = select 2
1
to 2
-14
1111 = select 2
16
. . .to 2
1
3
ENABLE INPUT EXPONENT BITS.
Enable the exponent bits from the input to be added to the attenuation control bits and routed to the channel(s).
2
ENABLE RANGE CONTROL EXPONENT BITS.
Enable the attenuator control register (accumulator MSBs) bits to be added to the exponent bits from the input and routed to the
channel(s).
1
ENABLE RANGE CONTROL.
1 = enable the range control.
0 = disable the range control (including timers).
0
ENABLE RANGE CONTROL BITS
Enable changes in the attenuator control register (if this bit is cleared, the timers still run but changes to the register are inhibited.
NOTE:
The range control can be enabled by writing to bit 0 or bit 0 can be set by SYNCInX to start updates. See IWA = 0*05h. Timing reset
by SYNCInX is enabled by bits 0 and 16 of IWA = 0*05h.
TABLE 36. ADC RANGE CONTROL -- MAIN (IWA = 0*10h)
RESET STATE = 0x00000000h
(Continued)
P(31:0)
FUNCTION
TABLE 37. TIME SLOT PERIOD, DELAY FROM SYNCInX TO START OF INTEGRATION (IWA = 0*11h)
RESET STATE = 0x00000000h
THIS
CONTROL IS SHARED FOR AIN/BIN AND FOR CIN/DIN
P(31:0)
FUNCTION
31:16
SYNC DELAY.
Delay from SYNC (external or counter generated) to the start of integration. Range of delay is 1 to 65536, load with the desired value
minus 1. Delay in input samples or clocks as selected by bit 14, IWA = 0*10h.
15:0
SLOT PERIOD.
Time interval between counter generated SYNCs in samples or clocks as selected by bit 14, IWA = 0*10h. Range for period is 2 to
65536, load with period minus 1.
TABLE 38. NUMBER OF INTEGRATIONS PER SLOT, INTEGRATION TIME (IWA = 0*12h)
RESET STATE = 0x00000000h
THIS CONTROL IS SHARED FOR AIN/BIN AND FOR CIN/DIN
P(31:0)
FUNCTION
31:16
NUMBER OF INTEGRATIONS PER SLOT.
Number of input magnitude integration periods per slot. Range is 1 to 32768, load with number of integrations minus 1.
15:0
INTEGRATION TIME.
Number of input samples to average before making an upper or lower threshold decision in samples or clocks as selected by bit 14,
IWA = 0*10h. Range is 2 to 65536, load with samples minus 1.
ISL5416
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