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參數(shù)資料
| 型號： | ISL5416KIZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, LEAD FREE, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 14/71頁 |
| 文件大?。?/td> | 1128K |
| 代理商： | ISL5416KIZ |
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14
Back-end Routing
FIR Filter Blocks
There are two programmable FIR filters in each channel.
The main function of the first filter, FIR1, is to reduce the CIC
output sample rate and maximize the efficiency of the
second filter, FIR2. FIR2 provides the final filtering for the
channel of interest. FIR1 can compute up to 32 taps and has
programmable 20-bit coefficients, 20-bit data inputs, and 24-
bit outputs. FIR2 can compute up to 64 taps and has
programmable 20-bit coefficients, 20-bit input data, and 24-
bit output data. FIR1 can compute 4 filter taps per clock and
FIR2 can compute 8. All of the available taps can be utilized
if the overall decimation through the CIC and FIRs is 8 or
more. The impulse response of each FIR can be symmetric
or asymmetric. The decimation for the each FIR is
programmable from 1 to 8.
To maximize dynamic range, the output bit width of the CIC
and each FIR is 24 bits. A programmable gain stage is
provided before each FIR to compensate for losses in
preceding stages and round to the 20-bit FIR input bit width.
Gains of 1, 2, 4, or 8 can be programmed. Saturation logic is
provided to prevent overflow.
FIR1 includes a half-band filter mode where a fixed center
coefficient of 0.5 is added and the zero valued half-band
coefficients are skipped in the computation. This allows FIR1
to compute a 15-tap half-band filter in two clock cycles or a
31-tap half-band filter in four clock cycles.
NOTE:
When loading halfband coefficients, the coefficients must be
centered around the fixed center coefficient, e.g. if there are
23 taps, three compute clocks are required, there are 11 on
either side of the center and multiplier 1 computes C0, C2,
C4, multiplier 2 C6, C8, C10, etc.
If there are 19 coefficients, multiplier 2 computes C4, C6, C8
and multiplier 1 computes Z, C0, and C2, i.e. an extra zero
valued coefficient must be added at each end of the
coefficient set to center the coefficients at the fixed
coefficient.
The filters will have unity gain if the sum of all coefficients is
equal to 1 for coefficient bit weighting 2
0
. . . 2
-19
MAG
AGC
LOOP
FILTER
FIR2
MUX
AGC
MULT
M
U
X
FROM
CIC
GAIN
I
Q
FIR1
G
G
EXTERNAL AGC GAIN
MAG
DETECT
1X
2X
4X
8X
1X
2X
4X
8X
FIFO
IHBF
HOIF
UP TO 32 TAPS
4 TAPS/CLK
HBF MODE
8 TAPS/CLK
UP TO 64 TAPS
CIC
BYPASS
CASCADED
CHANNELS
I
Q
ISL5416
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