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參數(shù)資料
| 型號： | ISL5416KIZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, LEAD FREE, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 32/71頁 |
| 文件大?。?/td> | 1128K |
| 代理商： | ISL5416KIZ |
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32
Tables of Top Level Registers
In the tables below “reset state” indicates the register
contents after a HW reset or a SW hard reset. Unless
noted, a soft channel reset does not clear register
contents. A soft channel reset does clear the slave
registers of a master/slave pair (such as channel data
path control) but does not clear the master.
This register controls the output SYNC signal polarity, the
output clock rate and polarity, output data modes, and
channel cascading.
TABLE 15. COMMON OUTPUT CONTROL FUNCTIONS (GWA = 0000h)
RESET STATE = 0x00000001h
P(31:0)
FUNCTION
31
ENABLE SERIAL OUTPUT.
1 = serial output mode is enabled. The DOUT parallel data bus is replaced with 4 serial output busses -- one per channel. See 0*06h
- 0*08h and Table 30.
30
RESERVED. Set to 0.
29
SCLK RESET.
1 = serial clock divider is reset by SYNCInX if the reset serial output bit is set in IWA = *000h, bits 13 or 29 of any of the 4 channels.
28
SCLK POLARITY.
1 = Low to High transitions at the center of the data bit.
0 = High to Low transitions at the center of the data bit.
27:25
SCLK RATE.
000 = SCLK DIsabled.
001 = input clock rate.
010 = input clock rate / 2.
011 = input clock rate / 4.
100 = input clock rate / 8.
101 = input clock rate /16.
24:21
RESERVED. Set to 0.
20
ROUTE CHANNEL 2 TO CHANNEL 3.
1 = route the output of FIR2 of channel 2 to the input of the CIC to FIR1 gain block in channel 3.
19
ROUTE CHANNEL 1 TO CHANNEL 2.
1 = route the output of FIR2 of channel 1 to the input of the CIC to FIR1 gain block in channel 2.
18
ROUTE CHANNEL 0 TO CHANNEL 1.
1 = route the output of FIR2 of channel 0 to the input of the CIC to FIR1 gain block in channel 1.
17
CHANNEL 0 EXTERNAL AGC SOURCE SELECT.
0 = when bit 14 is set, Channel 1 controls Channel 0 gain.
1 = when bit 14 is set, Channel 3 controls Channel 0 gain.
16
CHANNEL 2 EXTERNAL/INTERNAL GAIN CONTROL.
1 = Channel 2 gain is controlled by Channel 3.
15
CHANNEL 1 EXTERNAL/INTERNAL GAIN CONTROL.
1 = Channel 1 gain is controlled by Channel 3.
14
CHANNEL 0 EXTERNAL/INTERNAL GAIN CONTROL.
1 = Channel 0 gain is controlled by Channel 3 or Channel 1 depending on the state of bit 17.
13
CLKO2 OR INTRPT.
1 = CLKO2/INTRPT is INTRPT (2 clock period wide pulse).
0 = CLKO2/INTRPT is CLKO2.
NOTE: For INTRPT IWA = 0*0Ah, bit 31 must be set for the channel that is the interrupt source..
12
FSYNCX POLARITY.
0 = active high
1 = active low.
ISL5416
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