參數(shù)資料
型號: ISL5216
廠商: Intersil Corporation
英文描述: Four-Channel Programmable Digital DownConverter
中文描述: 四通道可編程數(shù)字下變頻器
文件頁數(shù): 41/65頁
文件大?。?/td> 1384K
代理商: ISL5216
41
TABLE 26. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 1 (IWA = *015h)
P(31:0)
FUNCTION
31:24
Fourth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 31:24.
23:16
Third serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 23:16.
15:8
Second serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 15:8.
7:0
First serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D.
Bit
Function
7
Sync generated. When set, a sync pulse is generated with the data slot (Serial Data Output 1 only, i.e., the sync is only
associated with Output 1). Set to zero for Output 2, SD2x.
6:3
Word width/format. All
fi
xed point data is twos complement. The data is rounded (asymmetrically, with saturation) to the
desired number of bits.
0000
0-bit,
fi
xed point (actually 1-bit position is used).
0001
4-bit,
fi
xed point.
0010
6-bit,
fi
xed point.
0011
8-bit,
fi
xed point.
0100
10-bit,
fi
xed point.
0101
12-bit,
fi
xed point.
0110
16-bit,
fi
xed point.
0111
20-bit,
fi
xed point.
1000
24-bit,
fi
xed point .
1001
32-bit
fi
xed (8 LSBs are zeroed).
1010
32-bit,
fl
oating point, IEEE format.
All other codes are invalid.
Note: Floating point format is only available on the Serial Data Output 1. Code 1010 is invalid on Serial Data Output 2.
2:0
Data type
000
Zeros
001
I1 (data routed from FIFO and AGC path).
010
Q1 (data routed from FIFO and AGC path).
011
Magnitude of I1/Q1.
100
Phase (or d
φ
/dt) of I1/Q1.
I2 (data routed directly from the
fi
lter processor).
101
110
Q2 (data routed directly from the
fi
lter processor).
111
AGC gain of I1/Q1 path.
The
fi
lter processor must be programmed appropriately to route the data to I1/Q1 or I2/Q2.
NOTE:
Disable a slot by setting the 8-bit word to 00h. When disabled, a slot still uses one clock period. If, for example, the slots are
programmed to 16-bit, disabled, 16-bit, there would a one clock idle period between the two 16-bit data words.
If a new data sample occurs before the current set of data has been output, the new data will preempt the output and the first slot of
the new data will begin immediately. If a late sync was programmed, it will not occur.
0123456789ABCDEF0123456789ABCDEF
I, Q
012345678901234567890123ZZZZZZZZ
MAG
Z12345678901234567890123ZZZZZZZZ (MSB zero unless shifted)
PH
012345678901234567ZZZZZZZZZZZZZZ
AGC
Z12345678901234567ZZZZZZZZZZZZZZ (MSB zeroed)
TABLE 27. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 2 (IWA = *016h)
P(31:0)
FUNCTION
31:24
Set to zero.
23:16
Seventh serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 23:16.
15:8
Sixth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 15:8.
7:0
Fifth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 7:0.
ISL5216
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