參數(shù)資料
型號(hào)： ISL5216
廠商： Intersil Corporation
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： 四通道可編程數(shù)字下變頻器
文件頁(yè)數(shù)： 19/65頁(yè)
文件大小： 1384K
代理商： ISL5216
19
Instruction Bit Fields
INSTRUCTION BIT FIELDS
BIT
POSITIONS
FUNCTION
DESCRIPTION
8:0
Instruction
Instruction Field Bit Mapping
Bit
8
7
6
5
4
3
2
1
0
Type
WAIT
0
0
X
X
X
X
C
C
C
FIR
0
1
Start
IncrRS
DecrSel
DecrEn
LdLp
DecrLp
EnU/C
JUMP
(NOPs and loading the loop counter are special cases of the FIR instruction).
XXXX
= ignored.
1
J
J
J
J
J
C
C
C
JJJJJ
= jump destination (sequence step number).
CCC
= condition code.
000
= ! (waitcount
≥
threshold) -- See IWA = *00Ch, bits 9:0 for threshold details.
= waitcount
≥
threshold -- See IWA = *00Ch, bits 9:0 for threshold details.
= loop counter
≠
0.
= loop counter = 0.
001
010
011
100
= ! (RSCO) (RSCO - resampler NCO carry output).
101
= RSCO.
110
= sync (if enabled) or
μ
P controlled bit.
= always.
111
Start
= load parameters and start
fi
lter computation, set to zero for no-ops, loop counter loads.
IncrRS
= increment resampler during this
fi
lter.
Increments on start or at each FIR output depending on
μ
Pcontrol bit.
= selects between two decrement values for the wait counter.
DecrSel
DecrEn
= decrement wait count on starting this instruction.
LdLp
= load loop counter with the data in the I(20:9) bit
fi
eld.
The start bit should not be set when this bit is set.
DecrLp
= decrement loop counter on starting this instruction.
EnU/C
= enable U/C counter with this FIR.
This multiplies the data by 1, j, -1, -j.
The multiplication factor changes each time the
fi
lter runs.
14:9
FIR Type
FIR Parameter Bit Fields
14:9
FIR type.
000000
NOP.
000001
Decimating FIR, Even Symmetric, Even # Taps.
000010
Decimating FIR, Even Symmetric, Odd # Taps.
000011
Decimating FIR, Odd Symmetric, Even # Taps.
000100
Decimating FIR, Odd Symmetric, Odd # Taps.
000101
Decimating FIR, Asymmetric.
001000
Resampling FIR, Asymmetric.
001001
Interpolating HBF.
100000
NOTES:
14. Regular interpolation FIRs are successive runs of a FIR with no data address increment, but with
coefficient start address increments.
15. Decimating HBFs are even symmetric, odd number of taps but with different data step sizes.
16. U/C FIR is a normal FIR with the U/C bit enabled.
17. Other codes may be added in the future.
Decimating FIR, Complex (Asymmetric).
17:15
Steps per FIR
Specifies the number of steps per FIR instruction sequence (load with value minus 1)
(set to 0 for all FIR types except complex which is set to 1).
ISL5216
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參數(shù)描述
ISL5216_05 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Four-Channel Programmable Digital DownConverter
ISL5216_07 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter
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ISL5216KI 功能描述:上下轉(zhuǎn)換器 QUAD DIGITAL DOWNCONVERTER,IND TEMP,0.8M RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
ISL5216KI-1 功能描述:上下轉(zhuǎn)換器 QUAD DIGITAL DOWNCONVERTER,IND TEMP,1.OMM PITCH BGA PACKAG RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
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