參數(shù)資料
型號(hào)： ISL5216
廠商： Intersil Corporation
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： 四通道可編程數(shù)字下變頻器
文件頁(yè)數(shù)： 21/65頁(yè)
文件大?。?/td> 1384K
代理商： ISL5216
21
63
Reserved
Set to 0.
66:64
Coefficient Memory
Block Size
66:64
Memory Block Size
0
8
1
16
2
32
3
64
4
128
5
256
6
512
7
(Modulo addressing can be used, but is usually not needed. If not needed this bit field can always be
set to 7).
1024
75:67
Number of FIR
Outputs
Number of FIR outputs (range is 1 to 512, load w/ desired value minus 1).
This is usually equal to the total decimation that follows the filter.
84:76
Read Address
Pointer Step
Read address pointer step (for next run). This is usually equal to the filter decimation times the number
of outputs from the instruction.
93:85
Initial Address Offset
Initial address offset (to ADDRB). This is the offset from the start address to other end of filter.
For symmetric filters, usually equal to -1 x (number of taps -1).
95:94
Reserved
Set to 0
104:96
Memory Reads Per
FIR Output
This is based on the number of taps (load with value below minus 1).
Type
Value
Symmetric, even number of taps
(taps/2) or
fl
oor((taps+1)/2).
Symmetric, odd number of taps
(taps+1)/2 or
fl
oor((taps+1)/2).
Decimating HBF
(taps+5)/4.
Asymmetric
taps.
Complex
taps .
Resampling
taps/phase (six taps per phase for the ROM’d coef
fi
cients provided).
Interpolating HBF
(taps+5)/4-1 .
106:105
Clocks Per
Memory Read
Set to 0 for all but complex FIR, which is set to 1.
115:107
Data Memory
Step Size 1
(ADDRA) Step size for all but the last tap computation of the FIR.
Set to -2 for HBF, -1 otherwise.
117:116
Data Memory
Step Size 2
(ADDRA) Step size for last tap computation. Set to -1.
117:116
Step size
0
0
1
-1
2
-2
3
step size value.
119:118
Data Memory
Address Offset Step
(ADDRB) Step size for opposite end of symmetric filter. Set to +2 for Decimating HBF, to +1 for others
(the B data is not used for asymmetric, resampling, and complex filters).
122:120
Coefficient Memory
Step Size
(ADDRC) Usually set to 1.
122:120
Step size
0
0
1
1
2
2
3
4
4
8
5
16
6
32
7
64
INSTRUCTION BIT FIELDS (Continued)
BIT
POSITIONS
FUNCTION
DESCRIPTION
ISL5216
相關(guān)PDF資料
PDF描述
ISL5217EVAL1 Quad Programmable Up Converter
ISL5217KI Quad Programmable Up Converter
ISL5217 Quad Programmable Up Converter
ISL5217KIZ Quad Programmable Up Converter
ISL5314INZ Direct Digital Synthesizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISL5216_05 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital DownConverter
ISL5216_07 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter
ISL5216EVAL1 功能描述:EVALUATION BOARD FOR ISL5216KI RoHS:是 類別:RF/IF 和 RFID >> RF 評(píng)估和開(kāi)發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796
ISL5216KI 功能描述:上下轉(zhuǎn)換器 QUAD DIGITAL DOWNCONVERTER,IND TEMP,0.8M RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
ISL5216KI-1 功能描述:上下轉(zhuǎn)換器 QUAD DIGITAL DOWNCONVERTER,IND TEMP,1.OMM PITCH BGA PACKAG RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
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