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參數(shù)資料
| 型號(hào)： | ISL1209 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Power RTC with Battery Backed SRAM and Event Detection |
| 中文描述： | 低功耗RTC與電池供電SRAM和事件檢測(cè) |
| 文件頁(yè)數(shù)： | 17/24頁(yè) |
| 文件大?。?/td> | 416K |
| 代理商： | ISL1209 |
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17
FN6109.1
September 27, 2005
Once the registers are set, the following waveform will be
seen at IRQ-:
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
User Registers
Addresses [12h to 13h]
These registers are 2 bytes of battery-backed user memory
storage.
I
2
C Serial Interface
The ISL1209 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is the master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL1209
operates as a slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 12). On power up of the ISL1209, the SDA pin is in
the input mode.
All I
2
C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL1209 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 12). A START condition is ignored during the power-
up sequence.
All I
2
C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 12). A STOP condition at the end
of a read operation or at the end of a write operation to
memory only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).
The ISL1209 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL1209 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
ALARM
REGISTER
BIT
DESCRIPTION
7 6 5 4 3 2 1 0 HEX
SCA
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA
0 0 0 0 0 0 0 0
00h Minutes disabled
HRA
0 0 0 0 0 0 0 0
00h Hours disabled
DTA
0 0 0 0 0 0 0 0
00h Date disabled
MOA
0 0 0 0 0 0 0 0
00h Month disabled
DWA
0 0 0 0 0 0 0 0
00h Day of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION
7 6 5 4 3 2 1 0 HEX
INT
1 1 x x 0 0 0 0
x0h Enable Alarm and Int
Mode
60 sec
RTC and alarm registers are both “30” sec
ISL1209
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| ISL1209_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM and Event Detection |
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