- 您現在的位置：買賣IC網 > PDF目錄384519 > ISL1209 (Intersil Corporation) Low Power RTC with Battery Backed SRAM and Event Detection PDF資料下載
參數資料
| 型號： | ISL1209 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Power RTC with Battery Backed SRAM and Event Detection |
| 中文描述： | 低功耗RTC與電池供電SRAM和事件檢測 |
| 文件頁數： | 16/24頁 |
| 文件大?。?/td> | 416K |
| 代理商： | ISL1209 |
16
FN6109.1
September 27, 2005
DIGITAL TRIMMING REGISTER (DTR <2:0>)
The digital trimming bits DTR0, DTR1, and DTR2 adjust the
average number of counts per second and average the ppm
error to achieve better accuracy.
DTR2 is a sign bit. DTR2 = “0” means frequency
compensation is >0. DTR2 = “1” means frequency
compensation is <0.
DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -60ppm to +60ppm can be represented by
using these three bits (see Table 13).
Alarm Registers
Addresses [0Ch to 11h]
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
Single Event Mode
is enabled by setting the ALME bit to
“1”, the IM bit to “0”, and disabling the frequency output.
This mode permits a one-time match between the alarm
registers and the RTC registers. Once this match occurs,
the ALM bit is set to “1” and the IRQ output will be pulled
low and will remain low until the ALM bit is reset. This can
be done manually or by using the auto-reset feature.
Interrupt Mode
is enabled by setting the ALME bit to “1”,
the IM bit to “1”, and disabling the frequency output. The
IRQ output will now be pulsed each time an alarm occurs.
This means that once the interrupt mode alarm is set, it
will continue to alarm for each occurring match of the
alarm and present time. This mode is convenient for
hourly or daily hardware interrupts in microcontroller
applications such as security cameras or utility meter
reading.
To clear an alarm, the ALM bit in the status register must be
set to “0” with a write. Note that if the ARST bit is set to 1
(address 07h, bit 7), the ALM bit will automatically be cleared
when the status register is read.
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1 – Alarm set with single interrupt (IM=”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm registers as follows:
B. Also the ALME bit must be set as follows:
xx indicate other control bits
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ output low.
Example 2 – Pulsed interrupt once per minute (IM=”1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm registers as follows:
B. Set the Interrupt register as follows:
xx indicate other control bits
TABLE 13. DIGITAL TRIMMING REGISTERS
DTR REGISTER
ESTIMATED
FREQUENCY
PPM
DTR2
DTR1
DTR0
0
0
0
0 (default)
0
0
1
+20
0
1
0
+40
0
1
1
+60
1
0
0
0
1
0
1
-20
1
1
0
-40
1
1
1
-60
ALARM
REGISTER
BIT
DESCRIPTION
7
6
5
4
3
2
1
0
HEX
SCA
0
0
0
0
0
0
0
0
00h
Seconds disabled
MNA
1
0
1
1
0
0
0
0
B0h
Minutes set to 30,
enabled
HRA
1
0
0
1
0
0
0
1
91h
Hours set to 11,
enabled
DTA
1
0
0
0
0
0
0
1
81h
Date set to 1,
enabled
MOA
1
0
0
0
0
0
0
1
81h
Month set to 1,
enabled
DWA
0
0
0
0
0
0
0
0
00h
Day of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION
7
6
5
4
3
2
1
0
HEX
INT
0
1
x
x
0
0
0
0
x0h
Enable Alarm
ISL1209
相關PDF資料 |
PDF描述 |
|---|---|
| ISL1209IU10-TK | Low Power RTC with Battery Backed SRAM and Event Detection |
| ISL1209IU10Z | Low Power RTC with Battery Backed SRAM and Event Detection |
| ISL22416 | Low Noise, Low Power, SPI Bus, 128 Taps(低噪聲,低功率，SPI總線, 128抽頭電位器) |
| ISL22419 | Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only(低噪聲,低功率，SPI總線, 128抽頭電位器) |
| ISL22426 | Low Noise, Low Power, SPI Bus, 128 Taps(低噪聲,低功率，SPI總線, 128抽頭電位器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISL1209_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM and Event Detection |
| ISL1209EVAL | 制造商:Intersil Corporation 功能描述:ISL1209 EVALUATION BOARD - Bulk |
| ISL1209EVALZ | 制造商:Intersil Corporation 功能描述:ISL1209EVALZ (PB-FREE ) EVALUATION BOARD - ROHS COMPLIANT - Rail/Tube |
| ISL1209IP18 | 制造商:Intersil Corporation 功能描述:LOW POWER RTC WITH BATTERY BACKED SRAM PDIP 18 - Rail/Tube |
| ISL1209IU10 | 功能描述:IC RTC/CALENDAR I2C 10-MSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 實時時鐘 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:時鐘/日歷 特點:警報器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數據格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應商設備封裝:8-TDFN EP 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。