- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384519 > ISL1209 (Intersil Corporation) Low Power RTC with Battery Backed SRAM and Event Detection PDF資料下載
參數(shù)資料
| 型號： | ISL1209 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Power RTC with Battery Backed SRAM and Event Detection |
| 中文描述： | 低功耗RTC與電池供電SRAM和事件檢測 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 416K |
| 代理商： | ISL1209 |
11
FN6109.1
September 27, 2005
SRAM. The I
2
C serial interface is compatible with other
industry I
2
C serial bus protocols using a bidirectional data
signal (SDA) and a clock signal (SCL).
Oscillator Compensation
The ISL1209 provides the option of timing correction due to
temperature variation of the crystal oscillator for either
manufacturing calibration or active calibration. The total
possible compensation is typically -94ppm to +140ppm. Two
compensation mechanisms that are available are as follows:
1. An analog trimming (ATR) register that can be used to
adjust individual on-chip digital capacitors for oscillator
capacitance trimming. The individual digital capacitor is
selectable from a range of 9pF to 40.5pF (based upon
32.758kHz). This translates to a calculated
compensation of approximately -34ppm to +80ppm. (See
ATR description.)
2. A digital trimming register (DTR) that can be used to
adjust the timing counter by ±60ppm. (See DTR
description.)
Also provided is the ability to adjust the crystal capacitance
when the ISL1209 switches from V
DD
to battery backup
mode. (See Battery Mode ATR Selection for more details.)
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:13h]. The defined addresses and default values are
described in the Table 1. Address 09h is not used. Reads or
writes to 09h will not affect operation of the device but should
be avoided.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 4 sections. These are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (5 bytes): Address 07h to 0Bh.
3. Alarm (6 bytes): Address 0Ch to 11h.
4. User SRAM (2 bytes): Address 12h to 13h.
There are no addresses above 13h.
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 4 of address 07h) is set to
“1”.
A multi-byte read or write operation is limited to one
section per operation.
Access to another section requires a
new operation. A read or write can begin at any address
within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. A
sequential read will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read, the address remains at the previous address +1 so the
user can execute a current address read and continue
reading the next register.
It is not necessary to set the WRTC bit prior to writing into
the control and status, alarm, and user SRAM registers.
ISL1209
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL1209IU10-TK | Low Power RTC with Battery Backed SRAM and Event Detection |
| ISL1209IU10Z | Low Power RTC with Battery Backed SRAM and Event Detection |
| ISL22416 | Low Noise, Low Power, SPI Bus, 128 Taps(低噪聲,低功率，SPI總線, 128抽頭電位器) |
| ISL22419 | Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only(低噪聲,低功率，SPI總線, 128抽頭電位器) |
| ISL22426 | Low Noise, Low Power, SPI Bus, 128 Taps(低噪聲,低功率，SPI總線, 128抽頭電位器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL1209_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM and Event Detection |
| ISL1209EVAL | 制造商:Intersil Corporation 功能描述:ISL1209 EVALUATION BOARD - Bulk |
| ISL1209EVALZ | 制造商:Intersil Corporation 功能描述:ISL1209EVALZ (PB-FREE ) EVALUATION BOARD - ROHS COMPLIANT - Rail/Tube |
| ISL1209IP18 | 制造商:Intersil Corporation 功能描述:LOW POWER RTC WITH BATTERY BACKED SRAM PDIP 18 - Rail/Tube |
| ISL1209IU10 | 功能描述:IC RTC/CALENDAR I2C 10-MSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 實(shí)時時鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/日歷 特點(diǎn):警報(bào)器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。