參數(shù)資料
型號(hào)： ISD-SR3000
文件頁數(shù)： 33/120頁
文件大?。?/td> 1293K
代理商： ISD-SR3000
1-28
1—HARDWARE
ISD-SR3000
Voice Solutions in Silicon
Figure 1-20: SRAM Read Cycle
1.
This cycle may be either TI (Idle), T3 or T3H.
2.
0
< n < 7
3.
If n = 0, this cycle may be either TI (Idle) or T1 (with a new address). If n = 1, this cycle is T3H, and
address bus does not change its value.
4.
Data can be driven by an external device at T2W1, T2W, T2 and T3.
5.
For an 8-bit data bus, address lines are A0-15 and data lines are D0-7.
6.
WR0 and WR1 are not available if Expansion Memory is configured as ROM. WR1 is not available
if Expansion Memory is configured as 8-bit bus RAM.
Figure 1-21: CODEC Short Frame Timing
Note
: This cycle may be either TI (Idle), T2, T3 or T3H.
CTTL
A1-16
(Note 5)
EMCS
WR0-1
(Note 6)
D0-15
(Note 5)
T3
T1
T2W1
nxT2W
(Note 2)
T2
T3
nxT3H
(Note 3)
(Note 1)
Data In
t
Av
t
EMCSa
t
EMCSh
t
EMCSia
t
EMCSh
t
DIs
t
DIh
(Note 4)
Address
CTTL
CCLK
CFS0/
CDOUT
CDIN
t
CTp
t
CTp
t
CTp
t
CTp
t
CTp
t
CTp
4xt
CTp
t
CTp
t
CTp
t
CTp
t
CTp
4xt
CTp
t
CCLKa
t
CCLKh
t
CCLKia
t
CCLKh
t
FSa
t
FSh
t
CTp
t
CTp
t
FSia
t
FSh
t
CDIs
t
CDIh
BIT 7
BIT 7
t
CDOv
t
CDOh
t
CTp
t
CTp
4xt
CTp
t
CTp
t
CTp
t
CTp
t
CTp
4xt
CTp
t
CTp
t
CTp
t
CDOv
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