參數(shù)資料
型號： ISD-SR3000
文件頁數(shù)： 26/120頁
文件大?。?/td> 1293K
代理商： ISD-SR3000
1-21
1—HARDWARE
ISD-SR3000
ISD
1.3.3 SWITCHING CHARACTERISTICS
DEFINITIONS
All timing specifications in this section refer to 0.8V or 2.0V on the rising or falling edges of the
signals, as illustrated in Figure 1-12 through Figure 1-18, unless specifically stated otherwise.
Maximum times assume capacitive loading of 50pF. CLKIN crystal frequency is 4.096MHz.
Note
: CTTL is an internal signal and is used as a reference to explain the timing of other signals. See Fig-
ure 1-27
.
Figure 1-12:
Synchronous Output Signals (Valid, Active and Inactive)
Note
: Signal valid, active or inactive time, after a rising edge of CTTL or MWCLK.
Figure 1-13: Synchronous Output Signals (Valid)
Note:
Signal valid time, after a falling edge of MWCLK.
2.0V
0.8V
CTTL or
MWCLK
Signal
t
Signal
2.0V
2.0V
0.8V
MWCLK
Signal
t
Signal
0.8V
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