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| 型號(hào)： | INSTRUCTIN603EWP |
| 英文描述： | Optimizing the Instruction Execution on the 603e |
| 中文描述： | 優(yōu)化了603e的指令執(zhí)行 |
| 文件頁(yè)數(shù)： | 7/54頁(yè) |
| 文件大?。?/td> | 325K |
| 代理商： | INSTRUCTIN603EWP |
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RISC Microprocessor Division
Page 7
Like most other superscalar processors, the 603e features pipelined execution flow, in which the
processing of an instruction is split into discrete stages. Each stage is able to handle a different
instruction, allowing multiple instructions to be in execution at once. For example, it may take three
cycles for a floating-point instruction to complete (three-cycle latency), but if there are no stalls in the
floating-point pipeline, then a series of floating-point instructions can have a throughput of one
instruction per cycle.
The 603e processor core consists of a fetcher, a dispatcher, and five execution units: an integer unit
(IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system
register unit (SRU). An instruction queue (IQ) holds up to six instructions that are fetched in and
waiting for dispatch. A completion queue (CQ) holds up to five instructions that have dispatched and
are waiting to be finished and retired.
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