
RISC Microprocessor Division
Page 13
The dispatcher and completion unit control the execution of instructions. Interactions between the
dispatcher and completion unit and the various execution units can reduce potential stalls in the
instruction pipeline. In the next few slides, we discuss these interactions.
The dispatcher is capable of buffering up to 6 instructions (in the instruction queue). However,
instructions must dispatch in-order out of the dispatcher and only from the bottom two slots (an
exception to this rule occurs with branch folding, discussed later). If the instruction in the bottom slot is
not capable of dispatching, then the instruction in the second slot cannot, either. It is the job of the
dispatcher to determine whether or not an execution unit is capable of accepting an instruction. The
dispatcher will stall instruction dispatch when the instructions awaiting dispatch requires an execution
unit that is unavailable, or will stall the second instruction if both instructions awaiting dispatch need the
same execution resource.
The completion unit is capable of buffering up to 5 instructions (in the completion queue). The
completion unit records the proper order of dispatch to enforce in-order completion. While instructions
are being tracked, the completion unit also keeps a record of exceptions generated, speculation, out-of-
order finishing, etc. All instructions except folded branches must be tracked in the completion unit. The
completion unit assigns rename registers (up to 5 integer and 4 floating point) to the instructions as
they dispatch. The completion unit will stall the dispatcher if no appropriate rename register resources
are available. Additionally, if there are no slots available in the completion queue, the completion unit
will order the dispatcher to stall the dispatching of instructions.