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| 型號(hào)： | INSTRUCTIN603EWP |
| 英文描述： | Optimizing the Instruction Execution on the 603e |
| 中文描述： | 優(yōu)化了603e的指令執(zhí)行 |
| 文件頁(yè)數(shù)： | 46/54頁(yè) |
| 文件大小： | 325K |
| 代理商： | INSTRUCTIN603EWP |
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RISC Microprocessor Division
Page 46
The fast timing requirements of superscalar processors sometimes lead to unusual types of stalls.
If a load has spent only one cycle in the LSU EA slot before accessing the data cache, then it is
removed from the LSU after this access (assuming that the access is not canceled). However, if a load
spends more than one cycle in the LSU EA slot, then it will appear to remain in this slot (blocking
subsequent LSU instructions) even after the load has accessed the data cache. This block will remain
until the data becomes available (and the load is marked “finished” in the completion queue).
In
Figure 1
, A flows into the LSU EA slot and flows out in
Figure 2
. This allows C to be dispatched to
the LSU. However, because B is stalled in the LSU EA slot, in
Figure 3
when B accesses the data
cache it keeps its entry in the LSU EA slot in
Figure 4
. This stalls C and stalls dispatch of any
subsequent load/store instruction until the data for B returns from the BIU.
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