參數(shù)資料
型號(hào)： INSTRUCTIN603EWP
英文描述： Optimizing the Instruction Execution on the 603e
中文描述： 優(yōu)化了603e的指令執(zhí)行
文件頁(yè)數(shù)： 34/54頁(yè)
文件大?。?/td> 325K
代理商： INSTRUCTIN603EWP
RISC Microprocessor Division
Page 34
Clock 5
:
A
is gone from the completion queue, but a delay on FP rename register deallocation
prevents FP rename register 0 from being re-allocated.
B
is finished and permitted to retire.
C
steps to
the Normalizer stage.
D
is dispatched to the FP Multiplier stage and is allocated FP rename register 3.
At this point, all four FP rename registers are in use, which means
E
cannot be marked for dispatch this
cycle.
E
stalls in the IQ.
Clock 6
: FP rename register 0 is deallocated.
B
is gone, but its FP rename register deallocation is
delayed for one clock.
C
is finished and permitted to retire.
D
moves to the Adder stage.
E
is marked
for dispatch.
Clock 7
: FP rename register 1 is deallocated.
C
steps the FP wait stage.
D
steps to the Normalizer
stage.
E
is dispatched to the Multiplier stage and is allocated FP rename register 0. At this point, the
pattern of stalls repeats.
Again, note the dispatch stall during clock 3. This is caused by all of M/A/N stages being in use.
Also note the dispatch stall during clock 5. This is caused by all of the rename registers being tied up
(a rename register must be deallocated for one clock before it can be reused).
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