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| 型號： | IDT88P8344BHGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 28/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標準包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8344BHGI |
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34
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
4.4 Microprocessor interface to SPI-3 datapath
capture/insert configurable parameters
Enable insertion / capture of data to the SPI-3 or SPI-4 data stream (which
is dependent on the egress control register). For each direction, the following
are to be used:
- Data for insertion or data captured
- Data available: set when data is available. Asserted by device for capture,
asserted by microprocessor for insertion.
- LID: Logical Identifier of capture / insertion channel
- Length: length of data for insertion or capture
- Flags: SOP, EOP, address parity error, data parity error, packet error
Thereareseparateinstantiationsofmicroprocessorinsertcapturebuffersfor
SPI-3 and SPI-4.
Capture data fragment
Packets can be captured from the SPI-3-4 stream and directed towards the
microprocessor. The capture buffer can store only one 256 byte packet
fragment. When the buffer is full the DATA_AVAILABLE flag is set and a SPI-
3captureeventisgenerated.Theeventisdirectedtowardstheinterruptmodule.
Read packet data fragment
The microprocessor needs to read a buffer to capture a packet fragment. It
verifies the DATA_AVAILABLE flag in the SPI-3 capture control register.
Microprocessor reads the packet fragment and EOP, SOP, ERROR, LID and
LENGTHfieldsfromtheSPI-3datacapturebuffer.Microprocessorhandsover
controlofthecapturebufferwhenitclearstheDATA_AVAILABLEflagintheSPI-
3 data capture control register (Table 31 - SPI-3 data capture control register).
4.4.1 SPI-3 to ingress microprocessor interface
datapath
The diagram below shows the datapath through the device from the SPI-3
interface to the microprocessor capture interface.
The following is a description of the path taken by a fragment of data through
the device.
DataentersonaSPI-3interfaceinfragments.Fragmentsareofequallength
except the last fragment of a packet which may be shorter. The LP address is
in-band with the data. The fragment enters a SPI-3 ingress buffer. SPI-3 LP
address, error information, SOP, and EOP are stored with the fragment. The
LP address is mapped to a LID. The fragment is stored in LID allocated buffer
segments.
The Table 80, SPI-3 egress port descriptor table (64 entries) is consulted,
and the PFP decides to send this LID to the microprocessor capture port. Data
ismovedtothecapturebufferalongwiththeLPaddress.LID,errorinformation,
SOP, and EOP. The data available bit is set. Data and control information are
read from the relevant register space through the microprocessor interface.
Figure 23. SPI-3 ingress to microprocessor capture interface datapath
…
JTAG
uproc
Chip Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
SPI-4.2
Min: 80 MHz
Max: 400 MHz
Interf
ace
Bloc
k
Interf
ace
Bloc
k
SPI-3 /
LID map
SPI-4 /
LID map
Main
Memory
A
LID Counters Memory
6370 drw15
Figure 22 . Microprocessor data capture buffer
6370 drw28
flags
length
data[1]
data[2]
data[255]
lid
data[0]
SOP
EA
ED
PAR
EOP
not used
EA
ED
PAR
data parity error
address parity error
packet error
70
inser
tsequence
t
t+1
t+258
e
xtr
act
sequence
t
t+1
t+258
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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