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參數(shù)資料
| 型號(hào)： | ICS9214YGLF-T |
| 英文描述： | Rambus XDR Clock Generator |
| 中文描述： | Rambus公司的XDR時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大?。?/td> | 228K |
| 代理商： | ICS9214YGLF-T |
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8
Integrated
Circuit
Systems, Inc.
ICS9214
0809D—04/07/06
DC Characteristics - Outputs
TA = 0°C to +70°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Power within spec to
outputs within spec
SMBus or Mode Select
transition to outputs valid
and within spec
Differential output
crossing voltage
Output Voltage Swing
(peak-to-peak singled
ended)
undershoot.
Measured at ODCLK_T/C
MIN
TYP
MAX
UNITS
Power up latency
t
PU
3
ms
State transition latency
1
t
CO
3
ms
V
OX
Measured as shown in Fig.
3
Measured as shown in Fig.
3. Excludes over and
0.9
1.1
V
V
COS
300
350
mV
Absolute output low voltage
VOLABS
pins
0.85
V
Reference Voltage for
swing control current
Ratio of output low
current to reference
current at typical V
DD2.5
V
ISET
V
DD
= 2.3V, V
OUT
= 1V
0.98
1.02
V
I
OL
/I
REF
I
REF
is equal to V
ISET
/R
RC
.
Tolerance of R
RC
<=+/-1%.
6.8
7
7.2
-
Minimum current at
V
OLABS
I
OLABS
Measured at ODCLK_T/C
pins with termination per
Figure 3.
45
-
mA
Low-level output voltage
SMBus
Low-level output current
SMBus
V
OLSMB
I
OL
= 4 mA
-
0.4
V
I
OLSMB
V
OL
= 0.8 V
6
-
mA
Tristate output current
I
OZ
Differential clock output pins
-
50
μΑ
Notes:
There is no output latency or glitches if a value is written to an output register.
that is the same as its current contents.
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