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參數(shù)資料
| 型號： | ICS9214YGLF-T |
| 英文描述： | Rambus XDR Clock Generator |
| 中文描述： | Rambus公司的XDR時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 228K |
| 代理商： | ICS9214YGLF-T |
2
Integrated
Circuit
Systems, Inc.
ICS9214
0809D—04/07/06
Pin Descriptions
PIN #
PIN NAME
1
AVDD2.5
2
AGND
PIN TYPE
PWR
PWR
DESCRIPTION
2.5V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
This pin establishes the reference current for the differential
clock pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current.
Analog Ground pin for Core PLL
"True" reference clock input.
"Complementary" reference clock input.
Power supply, nominal 2.5V
Ground pin.
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
SMBus address bit 0 (LSB)
SMBus address bit 1
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Power supply, nominal 2.5V
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Ground pin.
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Ground pin.
Power supply, nominal 2.5V
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Ground pin.
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Power supply, nominal 2.5V
3
IREFY
OUT
4
5
6
7
8
9
10
AGND
CLK_INT
CLK_INC
VDD2.5
GND
SMBCLK
SMBDAT
PWR
IN
IN
PWR
PWR
IN
I/O
11
OE
IN
12
13
SMB_A0
SMB_A1
IN
IN
14
BYPASS#/PLL
IN
15
VDD2.5
PWR
16
ODCLK_C3
OUT
17
ODCLK_T3
OUT
18
GND
PWR
19
ODCLK_C2
OUT
20
ODCLK_T2
IN
21
22
GND
VDD2.5
IN
PWR
23
ODCLK_C1
OUT
24
ODCLK_T1
OUT
25
GND
PWR
26
ODCLK_C0
OUT
27
ODCLK_T0
OUT
28
VDD2.5
PWR
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