參數(shù)資料
型號(hào)： ICS1892Y-14
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁(yè)數(shù)： 99/148頁(yè)
文件大?。?/td> 816K
代理商： ICS1892Y-14
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Chapter 8
Management Register Set
ICS1892, Rev. D, 2/26/01
February 26, 2001
99
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.14.1
Node/Repeater Configuration (bit 19.15)
The Node/Repeater Configuration bit directly indicates the state of the NOD/REP input pin. When this bit is
logic:
Zero, the NOD/REP input pin is pulled down, which instructs the operation code to operate in Node
mode.
One, the NOD/REP input pin is pulled up, which instructs the ICS1892 to operate in Repeater mode.
There are two primary differences between Node mode and Repeater mode.
In Node mode:
– The SQE Test default setting is enabled.
– The Carrier Sense signal (CRS) is asserted in response to either transmit or receive activity.
In Repeater mode:
– The SQE Test default setting is disabled.
– The Carrier Sense signal (CRS) is asserted in response only to receive activity.
8.14.2
Hardware/Software Priority Status (bit 19.14)
The Hardware/Software Priority Status bit directly indicates the state of the HW/SW pin. When this bit is
logic:
Zero, the hardware pins have priority over the (software) register bits for establishing the ICS1892
configuration.
One, the (software) register bits have priority over the hardware pins for establishing the ICS1892
configuration.
8.14.3
Remote Fault (bit 19.13)
The ISO/IEC specification defines bit 5.13 as the Remote Fault bit, and bit 19.13 is functionally identical to
bit 5.13. The Remote Fault bit is set based on the Link Control Word received from the remote link partner.
When this bit is a logic:
Zero, it indicates the remote link partner does not detect a Link Fault.
One, it indicates to the ICS1892/STA that the remote link partner detects a Link Fault.
8.14.4
ICS Reserved (bits 19.12:2)
ICS reserves these bits for future use. Functionally, these bits are equivalent to an IEEE Reserved bit.
When each of these reserved bits is:
Read by an STA, the ICS1892 returns a logic zero.
Written to by an STA, the STA must use the default value specified in this data sheet.
In general, ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1892, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA
always write the default value of any reserved bits during all management register write operations.
相關(guān)PDF資料
PDF描述
ICS1893AF 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893Y-10 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩
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ICS2002Y Wavedec Digital Audio Codec
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1893 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893_09 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
ICS1893AF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AFI 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AFILF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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