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| 型號： | ICS1892Y-14 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁數(shù)： | 44/148頁 |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892Y-14 |
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ICS1892, Rev. D, 2/26/01
February 26, 2001
44
Chapter 7
Functional Blocks
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
7.3.4.2
PMA Receive Modules
The ICS1892 PMA Receive module provides the following two functions:
NRZI Decoding
– The Receive module performs the NRZI decoding on the serial bit stream received from the
Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. It converts the bit stream to a
unipolar, positive, binary format which the PMA subsequently passes it to the PCS.
– The PMA extracts the clock embedded in the serial data stream.
Receive Clock Recovery
The Receive Clock Recovery function consists of a phase-locked loop (PLL) that operates on the serial
data stream received from the PMD sublayer. This PLL automatically synchronizes itself to the clock
encoded in the serial data stream and then provides both a recovered clock and data stream to the PCS.
The Receive Clock PLL requires a clock reference to acquire lock. Without a clock source, it continually
searches for a reference signal. Therefore, when the ICS1892 does not detect the presence of any signal
on its receive channel, it uses a Transmit Clock function to generate a reference for the Receive Clock PLL.
This is TBD.
The PMA Link Monitoring function observes the Receive Clock PLL. If the Receive Clock PLL cannot
acquire ‘lock’ on the serial data stream, it asserts an error signal. The status of this error signal can be read
in the QuickPoll Detailed Status Register’s PLL Lock Error bit (bit 17.9). This bit is a latching high (LH) bit.
(For more information on latching high and latching low bits, see
Section 8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
In general, the ICS1892 PMA Link Monitor functions continually audit the state of the connection with the
remote link partner. They assert a receive channel error if a receive signal is not detected or if a PLL Lock
Error occurs. These errors, in turn, generate a link fault and force the link monitor functions to clear both the
Status Register’s Link Status bit (bit 1.2) and the QuickPoll Detailed Status Register’s Link Status bit (bit
17.0).
7.3.5
PCS Control Signal Generation
For the PCS sublayer, there are two control signals: a Carrier Sense signal (CRS) and a Collision Detect
signal (COL).
The CRS control signals is generated as follows:
1.
2.
When a logic zero is detected in an idle bit stream, the Receive Functions examine the ensuing bits.
When the Receive Functions find the first two non-contiguous zero bits, the
Receive state machine
moves into the Carrier Detect state.
As a result, the Boolean Receiving variable is set to TRUE.
Consequently, the Carrier Sense state machine moves into the Carrier Sense ‘on’ state, which asserts
the CRS signal.
If the PCS Functions:
a. Cannot confirm either the /I/J/ (IDLE, J) symbols or the /J/K/ symbols, the receive error signal
(RX_ER) is asserted, and the Receive state machine returns to the IDLE state. In IDLE, the
Boolean Receiving variable is set to FALSE, thereby causing the Carrier Sense state machine to
set the CRS signal to FALSE.
b. Can confirm the /I/J/K/ symbols, then the Receive state machine transitions to the ‘Receive’ state.
3.
4.
5.
The COL control signal is generated by the transmit modules. For details, see
Section 7.3.3.1, “PCS
Transmit Module”
.
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| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFI | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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