參數(shù)資料
型號： ICS1892Y-14
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 90/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-14
ICS1892, Rev. D, 2/26/01
February 26, 2001
90
Chapter 8
Management Register Set
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.12.1
Data Rate (bit 17.15)
The Data Rate bit indicates the ‘selected technology’. If the ICS1892 is in:
Hardware mode, the value of this bit is determined by the 10/100SEL input pin.
Software mode, the value of this bit is determined by the Data Rate bit 0.13.
When bit 17.15 is logic:
Zero, it indicates that 10-MHz operations are selected.
One, the ICS1892 is indicating that 100-MHz operations are selected.
Note:
This bit does not imply any link status.
8.12.2
Duplex (bit 17.14)
The Duplex bit indicates the ‘selected technology’. If the ICS1892 is in:
Hardware mode, the value of this bit is determined by the DPXSEL input pin.
Software mode, the value of this bit is determined by the Duplex Mode bit 0.8.
When bit 17.14 is logic:
Zero, it indicates that half-duplex operations are selected.
One, the ICS1892 is indicating that full-duplex operations are selected.
Note:
This bit does not imply any link status.
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