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參數(shù)資料
| 型號： | ICS1892Y-14 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁數(shù)： | 16/148頁 |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892Y-14 |
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ICS1892, Rev. D, 2/26/01
February 26, 2001
16
Chapter 4
Overview of the ICS1892
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
4.1
100Base-TX Operation
During 100Base-TX data transmission, the ICS1892 accepts packets from a MAC/repeater and inserts
Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The
ICS1892 encapsulates each MAC/repeater frame, including the preamble, with an SSD and an ESD. As
per the ISO/IEC Standard, the ICS1892 replaces the first octet of each MAC preamble with an SSD and
appends an ESD to the end of each MAC/repeater frame.
When receiving data from the medium, the ICS1892 removes each SSD and replaces it with the
pre-defined preamble pattern before presenting the nibbles to its MAC/Repeater Interface. When the
ICS1892 encounters an ESD in the data stream, signifying the end of the frame, it ends the presentation of
nibbles to its MAC/Repeater Interface. Therefore, the local MAC/repeater receives an unaltered copy of the
transmitted frame sent by the remote MAC/repeater.
During periods when MAC frames are being neither transmitted nor received, the ICS1892 signals and
detects the IDLE condition on the Link Segment. In the 100Base-TX mode, the ICS1892 transmit channel
sends a continuous stream of scrambled ones to signify the IDLE condition. Similarly, the ICS1892 receive
channel continually monitors its data stream and looks for a pattern of scrambled ones. The results of this
signaling and monitoring provide the ICS1892 with the means to establish the integrity of the Link Segment
between itself and its remote link partner and informing its Station Management Entity (STA) of the link
status.
For 100M data transmission, the ICS1892 MAC/Repeater Interface can be configured to provide either a
100M Media Independent Interface (MII) or a 100M Symbol Interface. With the Symbol Interface
configuration, the data stream bypasses the ICS1892 Physical Coding sublayer (PCS) and the following
results:
1.
The ICS1892 shifts the responsibility of performing the 4B/5B translation to the MAC/repeater. As a
result, the requirement is for a 5-bit data path between the MAC/repeater and the ICS1892.
The latency through the ICS1892 reduces. (The ICS1892 provides this 100M Symbol Interface
primarily for repeater applications for which latency is a critical performance parameter.)
2.
4.2
10Base-T Operation
During 10Base-T data transmission, the ICS1892 inserts only the IDL delimiter into the data stream. The
ICS1892 appends the IDL delimiter to the end of each MAC frame. It is not required to insert an SSD-like
delimiter because the 10Base-T preamble already has a Start-of-Frame delimiter (SFD).
When receiving data from the medium (such as a twisted-pair cable), the ICS1892 uses the preamble to
synchronize its receive clock. When the ICS1892 receive clock establishes lock, it presents the preamble
nibbles to its MAC/Repeater Interface. The 10M MAC/Repeater Interface can be configured as either a
10M MII, a 10M Serial Interface, or a Link Pulse Interface.
In 10M operations, during periods when MAC frames are being neither transmitted nor received, the
ICS1892 signals and detects Normal Link Pulses. This action allows the integrity of the Link Segment with
the remote link partner to be established and then reported to the ICS1892’s STA.
相關(guān)PDF資料 |
PDF描述 |
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| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
| ICS2002 | Wavedec Digital Audio Codec |
| ICS2002Y | Wavedec Digital Audio Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFI | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFILF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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