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參數資料
| 型號： | ICL7109 |
| 廠商： | Intersil Corporation |
| 英文描述： | 12-Bit,Microprocessor-Compatible A/D Converter(12位、微處理器兼容的A/D轉換器) |
| 中文描述： | 12位A/D轉換器，帶有三態(tài)二進制輸出 |
| 文件頁數： | 8/23頁 |
| 文件大小： | 227K |
| 代理商： | ICL7109 |
5-11
Detailed Description
Analog Section
Figure 2 shows the equivalent circuit of the Analog Section
for the ICL7109. When the RUN/HOLD input is left open or
connected to V+, the circuit will perform conversions at a
rate determined by the clock frequency (8192 clock periods
per cycle). Each measurement cycle is divided into three
phases as shown in Figure 3. They are (1) auto-zero (A-Z),
(2) signal integrate (INT) and (3) de-integrate (DE).
Auto-Zero Phase
During auto-zero three things happen. First, input high and
low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
C
AZ
to compensate for offset voltages in the buffer amplifier,
integrator, and comparator. Since the comparator is included
in the loop, the A-Z accuracy is limited only by the noise of
the system. In any case, the offset referred to the input is
less than 10
μ
V.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range of the inputs. At the end of this phase,
the polarity of the integrated signal is determined.
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged (during
auto-zero) reference capacitor. Circuitry within the chip
ensures that the capacitor will be connected with the correct
polarity to cause the integrator output to return to zero cross-
ing (established in Auto-Zero) with a fixed slope. The time
required for the output to return to zero is proportional to the
input signal.
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
1V below the positive supply to 1.5V above the negative sup-
ply. In this range, the system has a CMRR of 86dB typical.
However, care must be exercised to assure the integrator out-
put does not saturate. A worst case condition would be a large
positive common mode voltage with a near full-scale negative
differential input voltage. The negative input signal drives the
integrator positive when most of its swing has been used up
by the positive common mode voltage. For these critical appli-
cations the integrator output swing can be reduced to less
than the recommended 4V full scale swing with little loss of
accuracy. The integrator output can swing to within 0.3V of
either supply without loss of linearity.
+
-
+
DE-
DE+
C
INT
C
AZ
R
INT
BUFFER
A-Z
INT
-
+
A-Z
IN HI
COMMON
IN LO
35
33
34
DE-
DE+
INT
A-Z
37
C
REF+
36
REF IN+
C
REF
REF IN-
39
A-Z
A-Z
38
C
REF
-
30
31
32
TO ZERO CROSS
DETECTOR
DIGITAL SECTION
A-Z
DE(
±
)
INTEGRATOR
INT
BUFFER
COMPARATOR
REF OUT
6.2V
29
28
40
10
μ
A
V-
V+
AZ
INT
DE+
DE-
FROM CONTROL
LOGIC
DIGITAL SECTION
-
+
FIGURE 2. ANALOG SECTION OF ICL7109
ICL7109
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