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參數(shù)資料
| 型號： | ICL7109 |
| 廠商： | Intersil Corporation |
| 英文描述： | 12-Bit,Microprocessor-Compatible A/D Converter(12位、微處理器兼容的A/D轉(zhuǎn)換器) |
| 中文描述： | 12位A/D轉(zhuǎn)換器，帶有三態(tài)二進(jìn)制輸出 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 227K |
| 代理商： | ICL7109 |
5-14
MODE Input
The MODE input is used to control the output mode of the
converter. When the MODE pin is low or left open (this input
is provided with a pulldown resistor to ensure a low level
when the pin is left open), the converter is in its “Direct” out-
put mode, where the output data is directly accessible under
the control of the chip and byte enable inputs. When the
MODE input is pulsed high, the converter enters the UART
handshake mode and outputs the data in two bytes, then
returns to “direct” mode. When the MODE input is left high,
the converter will output data in the handshake mode at the
end of every conversion cycle. (See section entitled “Hand-
shake Mode” for further details).
STATUS Output
During a conversion cycle, the STATUS output goes high at
the beginning of Signal Integrate (Phase II), and goes low
one-half clock period after new data from the conversion has
been stored in the output latches. See Figure 3 for of this tim-
ing. This signal may be used as a “data valid” flag (data never
changes while STATUS is low) to drive interrupts, or for
monitoring the status of the converter.
RUN/HOLD Input
When the RUN/HOLD input is high, or left open, the circuit will
continuously perform conversion cycles, updating the output
latches after zero crossing during the Deintegrate (Phase III)
portion of the conversion cycle (See Figure 3). In this mode of
operation, the conversion cycle will be performed in 8192
clock periods, regardless of the resulting value.
FIGURE 4. DIGITAL SECTION
FIGURE 5. RUN/HOLD OPERATION
TEST
LATCH
CLOCK
POL
OR
12 11 10
9
8
7
6
5
4
3
2
1
17
3
4
5
6
7
8
9
10 11 12 13 14 15
16
2
26
22
23
24
25
21
27
STATUS
RUN/
HOLD
OSC OSC OSC BUF
IN
OUT SEL OSC
MODE
SEND
OUT
LOW ORDER
BYTE OUTPUTS
B
B
B
B
B
B
B
B
B
B
B
B
GND
1
18
19
20
LBEN
HBEN
CE/LOAD
TO
ANALOG
SECTION
COMP OUT
AZ
INT
DEINT (+)
DEINT (-)
CONVERSION
CONTROL LOGIC
OSCILLATOR
AND CLOCK
CIRCUITRY
HIGH ORDER
BYTE OUTPUTS
12-BIT COUNTER
14 LATCHES
14 THREE-STATE OUTPUTS
HANDSHAKE
LOGIC
INT
PHASE II
STATIC IN
HOLD STATE
7 COUNTS
AUTOZERO
PHASE I
MIN 1790 COUNTS
MAX 2041 COUNTS
DEINT TERMINATED
AT ZERO CROSSING
DETECTION
INTERNAL
CLOCK
INTERNAL
LATCH
STATUS
OUTPUT
RUN/HOLD
INPUT
INTEGRATOR
OUTPUT
ICL7109
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