參數(shù)資料
型號(hào)： ICL7109
廠商： Intersil Corporation
英文描述： 12-Bit,Microprocessor-Compatible A/D Converter(12位、微處理器兼容的A/D轉(zhuǎn)換器)
中文描述： 12位A/D轉(zhuǎn)換器，帶有三態(tài)二進(jìn)制輸出
文件頁(yè)數(shù)： 12/23頁(yè)
文件大?。?/td> 227K
代理商： ICL7109
5-15
If RUN/HOLD goes low at any time during Deintegrate (Phase
III) after the zero crossing has occurred, the circuit will imme-
diately terminate Deintegrate and jump to Auto-Zero. This fea-
ture can be used to eliminate the time spent in Deintegrate
after the zero-crossing. If RUN/HOLD stays or goes low, the
converter will ensure minimum Auto-Zero time, and then wait
in Auto-Zero until the RUN/HOLD input goes high. The con-
verter will begin the Integrate (Phase II) portion of the next
conversion (and the STATUS output will go high) seven clock
periods after the high level is detected at RUN/HOLD. See
Figure 5 for details.
Using the RUN/HOLD input in this manner allows an easy
“convert on demand” interface to be used. The converter may
be held at idle in auto-zero with RUN/HOLD low. When
RUN/HOLD goes high the conversion is started, and when
the STATUS output goes low the new data is valid (or trans-
ferred to the UART; see Handshake Mode). RUN/HOLD may
now be taken low which terminates deintegrate and ensures a
minimum Auto-Zero time before the next conversion.
Alternately, RUN/HOLD can be used to minimize conversion
time by ensuring that it goes low during Deintegrate, after zero
crossing, and goes high after the hold point is reached. The
required activity on the RUN/HOLD input can be provided by
connecting it to the Buffered Oscillator Output. In this mode
the conversion time is dependent on the input value
measured. Also refer to Intersil Application Note AN032 for a
discussion of the effects this will have on Auto-Zero
performance.
If the RUN/HOLD input goes low and stays low during Auto-
Zero (Phase I), the converter will simply stop at the end of
Auto-Zero and wait for RUN/HOLD to go high. As above, Inte-
grate (Phase II) begins seven clock periods after the high level
is detected.
Direct Mode
When the MODE pin is left at a low level, the data outputs
(bits 1 through 8 low order byte, bits 9 through 12, polarity and
over-range high order byte) are accessible under control of
the byte and chip enable terminals as inputs. These three
inputs are all active low, and are provided with pullup resistors
to ensure an inactive high level when left open. When the chip
enable input is low, taking a byte enable input low will allow
the outputs of that byte to become active (three-stated on).
This allows a variety of parallel data accessing techniques to
be used, as shown in the section entitled “Interfacing.” The
timing requirements for these outputs are shown in Figure 6
and Table 1.
It should be noted that these control inputs are
asynchronous with respect to the converter clock - the data
may be accessed at any time. Thus it is possible to access
the latches while they are being updated, which could lead to
erroneous data. Synchronizing the access of the latches
with the conversion cycle by monitoring the STATUS output
will prevent this. Data is never updated while STATUS is low.
Handshake Mode
The handshake output mode is provided as an alternative
means of interfacing the ICL7109 to digital systems where the
A/D converter becomes active in controlling the flow of data
instead of passively responding to chip and byte enable
inputs. This mode is specifically designed to allow a direct
interface between the ICL7109 and industry-standard UARTs
(such as the Intersil IM6402/3) with no external logic required.
When triggered into the handshake mode, the ICL7109 pro-
vides all the control and flag signals necessary to sequentially
transfer two bytes of data into the UART and initiate their
transmission in serial form. This greatly eases the task and
reduces the cost of designing remote data acquisition stations
using serial data transmission.
TABLE 1. DIRECT MODE TIMING REQUIREMENTS
(See Note 4 of Electrical Specifications)
DESCRIPTION
SYMBOL
MIN
TYP
MAX
UNITS
Byte Enable
Width
t
BEA
350
220
-
ns
Data Access
Time from Byte
Enable
t
DAB
-
210
350
ns
Data Hold Time
from Byte
Enable
t
DHB
-
150
300
ns
Chip Enable
Width
t
CEA
400
260
-
ns
Data Access
Time from Chip
Enable
t
DAC
-
260
400
ns
Data Hold Time
from Chip
Enable
t
DHC
-
240
400
ns
FIGURE 6. DIRECT MODE OUTPUT TIMING
DATA
VALID
DATA
VALID
DATA
VALID
t
CEA
t
BEA
t
DAB
t
DHB
t
DAC
t
DHC
CE/LOAD
AS INPUT
HBEN
AS INPUT
LBEN
AS INPUT
HIGH BYTE
DATA
LOW BYTE
DATA
= HIGH IMPEDANCE
ICL7109
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