參數(shù)資料
型號(hào)： ICL7109
廠商： Intersil Corporation
英文描述： 12-Bit,Microprocessor-Compatible A/D Converter(12位、微處理器兼容的A/D轉(zhuǎn)換器)
中文描述： 12位A/D轉(zhuǎn)換器，帶有三態(tài)二進(jìn)制輸出
文件頁(yè)數(shù)： 14/23頁(yè)
文件大小： 227K
代理商： ICL7109
5-17
Assuming the UART Transmitter Buffer Register is empty, the
SEND input will be high when the handshake mode is entered
after new data is stored. The CE/LOAD and HBEN terminals will
go low after SEND is sensed, and the high order byte outputs
become active. When CE/LOAD goes high at the end of one
clock period, the high order byte data is clocked into the UART
Transmitter Buffer Register. The UART TBRE output will now go
low, which halts the output cycle with the HBEN output low, and
the high order byte outputs active. When the UART has trans-
ferred that data to the Transmitter Register and cleared the
Transmitter Buffer Register, the TBRE returns high. On the next
ICL7109 internal clock high to low edge, the high order byte out-
puts are disabled, and one-half internal clock later, the HBEN
output returns high. At the same time, the CE/LOAD and LBEN
outputs go low, and the low order byte outputs become active.
Similarly, when the CE/LOAD returns high at the end of one
clock period, the low order data is clocked into the UART Trans-
mitter Buffer Register, and TBRE again goes low. When TBRE
returns to a high it will be sensed on the next ICL7109 internal
clock high to low edge, disabling the data outputs. One-half
internal clock later, the handshake mode will be cleared, and the
CE/LOAD, HBEN and LBEN terminals return high and stay
inactive (as long as MODE stays high).
With the MODE input remaining high as in these examples,
the converter will output the results of every conversion
except those completed during a handshake operation. By
triggering the converter into handshake mode with a low to
high edge on the MODE input, handshake output
sequences may be performed on demand. Figure 9 shows
a handshake output sequence triggered by such an edge.
In addition, the SEND input is shown as being low when the
converter enters handshake mode. In this case, the whole
output sequence for the first (high order) byte is similar to
the sequence for the second byte. This diagram also shows
the output sequence taking longer than a conversion cycle.
Note that the converter still makes conversions, with the
STATUS output and RUN/HOLD input functioning normally.
The only difference is that new data will not be latched
when in handshake mode, and is therefore lost.
Oscillator
The ICL7109 is provided with a versatile three terminal
oscillator to generate the internal clock. The oscillator may be
overdriven, or may be operated with an RC network or crystal.
The OSCILLATOR SELECT input changes the internal configu-
ration of the oscillator to optimize it for RC or crystal operation.
When the OSCILLATOR SELECT input is high or left open
(the input is provided with a pullup resistor), the oscillator is
configured for RC operation, and the internal clock will be of
the same frequency and phase as the signal at the
BUFFERED OSCILLATOR OUTPUT. The resistor and capac-
itor should be connected as in Figure 10. The circuit will oscil-
late at a frequency given by f = 0.45/RC. A 100k
resistor is
recommended for useful ranges of frequency. For optimum
60Hz line rejection, the capacitor value should be chosen
such that 2048 clock periods is close to an integral multiple of
the 60Hz period (but should not be less than 50pF).
ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED
INTEGRATOR
OUTPUT
INTERNAL
CLOCK
INTERNAL
LATCH
STATUS
OUTPUT
MODE
INPUT
INTERNAL
MODE
UART
NORM
SEND INPUT
(UART TBRE)
CE/LOAD OUTPUT
(UART TBRL)
HBEN
HIGH BYTE
DATA
LBEN
LOW BYTE
DATA
= DON’T CARE
= THREE-STATE HIGH IMPEDANCE
SEND
SENSED
SEND
SENSED
TERMINATES
UART MODE
DATA VALID
DATA VALID
FIGURE 8. HANDSHAKE - TYPICAL UART INTERFACE TIMING
ICL7109
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