參數(shù)資料
型號(hào)： ICL7109
廠(chǎng)商： Intersil Corporation
英文描述： 12-Bit,Microprocessor-Compatible A/D Converter(12位、微處理器兼容的A/D轉(zhuǎn)換器)
中文描述： 12位A/D轉(zhuǎn)換器，帶有三態(tài)二進(jìn)制輸出
文件頁(yè)數(shù)： 15/23頁(yè)
文件大?。?/td> 227K
代理商： ICL7109
5-18
When the OSCILLATOR SELECT input is low a feedback
device and output and input capacitors are added to the oscil-
lator. In this configuration, as shown in Figure 11, the oscillator
will operate with most crystals in the 1MHz to 5MHz range
with no external components. Taking the OSCILLATOR
SELECT input low also inserts a fixed
÷
58 divider circuit
between the BUFFERED OSCILLATOR OUTPUT and the
internal clock. Using an inexpensive 3.58MHz TV crystal, this
division ratio provides an integration time given by:
t
INT
= (2048 clock periods) x (t
CLOCK
) = 33.18ms where:
This time is very close to two 60Hz periods or 33ms. The
error is less than one percent, which will give better than
40dB 60Hz rejection. The converter will operate reliably at
conversion rates of up to 30 per second, which corresponds
to a clock frequency of 245.8kHz.
If at any time the oscillator is to be overdriven, the overdriv-
ing signal should be applied at the OSCILLATOR INPUT,
and the OSCILLATOR OUTPUT should be left open. The
internal clock will be of the same frequency, duty cycle, and
phase as the input signal when OSCILLATOR SELECT is
left open. When OSCILLATOR SELECT is at GND, the clock
will be a factor of 58 below the input frequency.
When using the ICL7109 with the IM6403 UART, it is
possible to use one 3.58MHz crystal for both devices. The
BUFFERED OSCILLATOR OUTPUT of the ICL7109 may be
used to drive the OSCILLATOR INPUT of the UART, saving
the need for a second crystal. However, the BUFFERED
OSCILLATOR OUTPUT does not have a great deal of drive
capability, and when driving more than one slave device
external buffering should be used.
Test Input
When the TEST input is taken to a level halfway between V+
and GND, the counter output latches are enabled, allowing
the counter contents to be examined anytime.
When the RUN/HOLD is low and the TEST input is
connected to GND, the counter outputs are all forced into the
high state, and the internal clock is disabled. When the
RUN/HOLD returns high and the TEST input returns to the
1
/
2
(V+ - GND) voltage (or to V+) and one clock is applied, all
the counter outputs will be clocked to the low state. This
allows easy testing of the counter and its outputs.
tCLOCK
-------------------------
=
ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED
INTERNAL
CLOCK
INTERNAL
LATCH
STATUS
OUTPUT
MODE
INPUT
INTERNAL
MODE
UART
NORM
SEND INPUT
CE/LOAD OUTPUT
HBEN
HIGH BYTE
DATA
LBEN
LOW BYTE
DATA
= DON’T CARE
= THREE-STATE HIGH IMPEDANCE
SEND
SENSED
SEND
SENSED
TERMINATES
UART MODE
DATA VALID
DATA VALID
= THREE-STATE WITH PULLUP
SEND
SENSED
LATCH PULSE INHIBITED
IN UART MODE
DEINT
PHASE III
STATUS OUTPUT
UNCHANGED IN
UART MODE
POSITVE TRANSITION CAUSES
ENTRY INTO
UART MODE
FIGURE 9. HANDSHAKE TRIGGERED BY MODE
ICL7109
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