參數(shù)資料
型號(hào): ICL7109
廠商: Intersil Corporation
英文描述: 12-Bit,Microprocessor-Compatible A/D Converter(12位、微處理器兼容的A/D轉(zhuǎn)換器)
中文描述: 12位A/D轉(zhuǎn)換器,帶有三態(tài)二進(jìn)制輸出
文件頁數(shù): 13/23頁
文件大?。?/td> 227K
代理商: ICL7109
5-16
Entry into the handshake mode is controlled by the MODE pin.
When the MODE terminal is held high, the ICL7109 will enter
the handshake mode after new data has been stored in the out-
put latches at the end of a conversion (See Figures 7 and 8).
The MODE terminal may also be used to trigger entry into the
handshake mode on demand. At any time during the conver-
sion cycle, the low to high transition of a short pulse at the
MODE input will cause immediate entry into the handshake
mode. If this pulse occurs while new data is being stored, the
entry into handshake mode is delayed until the data is stable.
While the converter is in the handshake mode, the MODE input
is ignored, and although conversions will still be performed,
data updating will be inhibited (See Figure 9) until the converter
completes the output cycle and clears the handshake mode.
When the converter enters the handshake mode, or when the
MODE input is high, the chip and byte enable terminals
become TTL-compatible outputs which provide the control
signals for the output cycle (See Figures 7, 8, and 9).
In handshake mode, the SEND input is used by the converter
as an indication of the ability of the receiving device (such as
a UART) to accept data.
Figure 7 shows the sequence of the output cycle with SEND
held high. The handshake mode (Internal MODE high) is
entered after the data latch pulse, and since MODE remains
high the CE/LOAD, LBEN and HBEN terminals are active as
outputs. The high level at the SEND input is sensed on the
same high to low internal clock edge that terminates the data
latch pulse. On the next low to high internal clock edge the
CE/LOAD and the HBEN outputs assume a low level, and the
high-order byte (Bits 9 through 12, POL, and OR) outputs are
enabled. The CE/LOAD output remains low for one full internal
clock period only, the data outputs remain active for 1
1
/
2
inter-
nal clock periods, and the high byte enable remains low for two
clock periods. Thus the CE/LOAD output low level or low to
high edge may be used as a synchronizing signal to ensure
valid data, and the byte enable as an output may be used as a
byte identification flag. With SEND remaining high the con-
verter completes the output cycle using CE/LOAD and LBEN
while the low order byte outputs (bits 1 through 8) are activated.
The handshake mode is terminated when both bytes are sent.
Figure 8 shows an output sequence where the SEND input is
used to delay portions of the sequence, or handshake to ensure
correct data transfer. This timing diagram shows the relation-
ships that occur using an industry-standard IM6402/3 CMOS
UART to interface to serial data channels. In this interface, the
SEND input to the ICL7109 is driven by the TBRE (Transmitter
Buffer Register Empty) output of the UART, and the CE/LOAD
terminal of the ICL7109 drives the TBRL (Transmitter Buffer
Register Load) input to the UART. The data outputs are paral-
leled into the eight Transmitter Buffer Register inputs.
INTEGRATOR
OUTPUT
INTERNAL
CLOCK
INTERNAL
LATCH
STATUS
OUTPUT
MODE
INPUT
INTERNAL
MODE
SEND
INPUT
CE/LOAD
HBEN
HIGH BYTE
DATA
LBEN
LOW BYTE
DATA
= DON’T CARE
ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED
MODE HIGH ACTIVATES
CE/LOAD, HBEN, LBEN
UART
NORM
SEND
SENSED
SEND
SENSED
TERMINATES
UART MODE
= THREE-STATE HIGH IMPEDANCE
= THREE-STATE WITH PULLUP
MODE LOW, NOT
IN HANDSHAKE MODE
DISABLES OUTPUTS CE/LOAD, HBEN, LBEN
DATA VALID
DATA VALID
FIGURE 7. HANDSHAKE WITH SEND HELD HIGH
ICL7109
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