參數(shù)資料
型號(hào)： HYB25D512800AT-7
英文描述： ?512Mb (64Mx8) DDR266A (2-3-3)?
中文描述： ？的512Mb（64Mx8）DDR266A（2-3-3）？
文件頁(yè)數(shù)： 44/76頁(yè)
文件大?。?/td> 1218K
代理商： HYB25D512800AT-7
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Page 44 of 76
2002-05-06
Power-Down
Power-down is entered when CK
E
is registered LO
W
(no accesses can be in progress). If power-down
occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down.
E
ntering power-down
deactivates the input and output buffers, excluding CK, CK and CK
E
. The DLL is still running in Power Down
mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Power-
down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur
before a Read command can be issued. In power-down mode, CK
E
Low and a stable clock signal must be
maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”.
H
owever, power-
down duration is limited by the refresh requirements of the device, so in most applications, the self refresh
mode is preferred over the DLL-disabled power-down mode.
The power-down state is synchronously exited when CK
E
is registered
H
I
GH
(along with a
N
op or Deselect
command). A valid, executable command may be applied one clock cycle later.
Power Down
t
IS
t
IS
CK
CK
CK
E
Command
N
o column
access in
progress
VALID
N
OP
VALID
Don’t Care
E
xit
power down
mode
E
nter Power Down mode
(Burst Read or
W
rite operation
must not be in progress)
N
OP
相關(guān)PDF資料
PDF描述
HYB25D512800AT-8 ?512Mb (64Mx8) DDR200 (2-2-2)?
HYB25M128160C-653 RAMBUS DRAM
HYB25M128160C-745 RAMBUS DRAM
HYB25M128160C-840 RAMBUS DRAM
HYB25M128160C-845 RAMBUS DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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HYB25DC512160CE-5 制造商:Infineon Technologies AG 功能描述: 制造商:QIMONDA 功能描述:
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