參數(shù)資料
型號： HYB18T512800AF-3S
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 47/117頁
文件大?。?/td> 2102K
代理商： HYB18T512800AF-3S
Data Sheet
47
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.16
Posted CAS
Posted CAS operation is supported to make command
and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. In this operation, the DDR2 SDRAM
allows a Read or Write command to be issued
immediately after the bank activate command (or any
time during the RAS to CAS delay time,
t
RCD
period).
The command is held for the time of the Additive
Latency (AL) before it is issued inside the device. The
Read Latency (RL) is the sum of AL and the CAS
latency (CL). Therefore if a user chooses to issue a
Read/Write command before the
t
RCD.MIN
, then AL
greater than 0 must be written into the EMR(1). The
Write Latency (WL) is always defined as RL - 1 (Read
Latency -1) where Read Latency is defined as the sum
of Additive Latency plus CAS latency (RL=AL+CL). If a
user chooses to issue a Read command after the
t
RCD.MIN
period, the Read Latency is also defined as
RL = AL + CL.
Figure 19
Activate to Read Timing Example: Read followed by a write to the same bank
Activate to Read delay <
t
RCD.MIN
: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
Figure 20
Read to Write Timing Example: Read followed by a write to the same bank
Activate to Read delay <
t
RCD.MIN
: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
Bank A
tRCD
CL = 3
AL = 2
RL = AL + CL = 5
WL = RL -1 = 4
PostCAS
CMD
DQ
DQS,
DQS
CK, CK
0
2
3
4
5
1
6
7
8
9
10
11
Dout0Dout1 Dout2Dout3
Din0
Din1 Din2
Din3
Read
Write
Bank A
tRCD
CL = 3
AL = 2
RL = AL + CL = 5
WL = RL -1 = 4
PostCAS3
CMD
DQ
DQS,
DQS
CK, CK
0
2
3
4
5
1
6
7
8
9
10
11
Read
Write
Din0
Din1
Din2
Din3
Dout0 Dout1Dout2 Dout3 Dout4 Dout5 Dout6 Dout7
12
相關(guān)PDF資料
PDF描述
HYB18T512800AC-37 M39012 MIL RF CONNECTOR
HYB18T512800AC-5 M39012 MIL RF CONNECTOR
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