參數(shù)資料
型號(hào): HYB18T512800AF-3S
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 14/117頁
文件大?。?/td> 2102K
代理商: HYB18T512800AF-3S
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Data Sheet
14
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
power down entry and exit and for self-refresh entry. Input
buffers excluding CKE are disabled during self-refresh.
CKE is used asynchronously to detect self-refresh exit
condition. Self-refresh termination itself is synchronous.
After
V
REF
has become stable during power-on and
initialisation sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh entry
and exit,
V
REF
must be maintained to this input. CKE must
be maintained HIGH throughout read and write accesses.
Input buffers, excluding CK, CK, ODT and CKE are disabled
during power-down
2
Pin Configuration and Block Diagrams
The pin configuration of a DDR2 SDRAM is listed by function in
Table 4
. The abbreviations used in the Pin#/Buffer
Type columns are explained in
Table 5
and
Table 6
respectively. The pin numbering for the FBGA package is
depicted in Figure 1 for
×
4, Figure 2 for
×
8 and Figure 3 for
×
16
.
Table 4
Ball#/Pin#
Pin Configuration of DDR SDRAM
Name
Pin
Type
Clock Signals
×
4/
×
8 organizations
E8
CK
F8
CK
Buffer
Type
Function
I
I
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Note:CK and CK are differential system clock inputs. All address
and control inputs are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossing of CK and CK (both
direction of crossing)
Clock Enable
Note:CKE HIGH activates and CKE LOW deactivates internal
clock signals and device input buffers and output drivers.
Taking CKE LOW provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-
Down (row Active in any bank). CKE is synchronous for
F2
CKE
I
SSTL
Clock Signals
×
16 organization
J8
CK
K8
CK
K2
CKE
Control Signals
×
4/
×
8 organizations
F7
RAS
G7
CAS
F3
WE
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
I
I
I
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Note:RAS, CAS and WE (along with CS) define the command
being entered.
Chip Select
Note:All command are masked when CS is registered HIGH. CS
provides for external rank selection on systems with
multiple memory ranks. CS is considered part of the
command code.
G8
CS
I
SSTL
相關(guān)PDF資料
PDF描述
HYB18T512800AC-37 M39012 MIL RF CONNECTOR
HYB18T512800AC-5 M39012 MIL RF CONNECTOR
HYB18T512800AC DDR2 Registered Memory Modules
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